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E-L6219DS013TR
Stepper Motor Driver
September 2008 Rev 13 1/16
L6219Stepper motor driver
Features Able to drive both windings of bipolar stepper
motor Output current up to 750 mA each winding Wide voltage range: 10 V to 46 V Half-step, full-step and microstepping mode Built-in protection diodes Internal PWM current control Low output saturation voltage Designed for unstabilized motor supply voltage Internal thermal shutdown
DescriptionThe L6219 is a bipolar monolithic integrated
circuits intended to control and drive both winding
of a bipolar stepper motor or bidirectionally control
two DC motors.
The L6219 with a few external components form a
complete control and drive circuit for LS-TTL or
microprocessor controlled stepper motor system.
The power stage is a dual full bridge capable of
sustaining 46V and including four diodes for
current recirculation.
A cross conduction protection is provided to avoid
simultaneous cross conduction during switching
current direction.
An internal pulse-width-modulation (PWM)
controls the output current to 750 mA with peak
startup current up to 1 A.
Wide range of current control from 750 mA (each
bridge) is permitted by means of two logic inputs
and an external voltage reference. A phase input
to each bridge determines the load current
direction. A thermal protection circuitry disables
the outputs if the chip temperature exceeds safe
operating limits.
Table 1. Device summary
Contents L62192/16
Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1 Input logic (I0 and I1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Current sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Single-pulse generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6 VS, VSS, VRef . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
L6219 List of tables
3/16
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Electrical characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Current levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
List of figures L6219
4/16
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. SO24/PDIP24 pins connection (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Principle operating sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. SO24 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. PDIP24 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
L6219 Block diagram
5/16
1 Block diagram
Figure 1. Block diagram
Table 2. Absolute maximum rating
Block diagram L6219
6/16
Figure 2. SO24/PDIP24 pins connection (top view)
Table 3. Pin functions
L6219 Block diagram
7/16
Note: ESD on GND, VS, VSS, OUT 1 A and OUT 2 A is guaranteed up to 1.5 KV (human body
model, 1500 W, 100 pF).
Figure 3. Timing diagram
Table 3. Pin functions (continued)
Table 4. Thermal data With minimized copper area.
Block diagram L6219
8/16
Table 5. Electrical characteristcs
(Tj = 25 °C, VS = 46 V , VSS = 4.75 V to 5.25 V, VREF = 5 V, unless otherwise
specified) See Figure5 To reduce the switching losses the base bias of the bridge's low side NPN transistor is proportional to the
DAC output, then the output current driving capability is also proportional to the DAC output voltage, having
as reference 750 mA with VREF = 5 V and DAC =100%. For example using VREF = 2 V and DAC = 67% the
output maximum current driving capability will become 750 mA*(2V*0.67)/(5V*1) = 200 mA.
