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DVIULC6-4SC6
Ultralow capacitance ESD protection
September 2012 Doc ID 11599 Rev 4 1/12
DVIULC6-4SC6Ultralow capacitance ESD protection
Datasheet production data
Features 4-line ESD protection (IEC 61000-4-2) Protects VBUS when applicable Ultralow capacitance: 0.6 pF at 825 MHz Fast response time compared with varistors SOT23-6L package RoHS compliant
Benefits ESD standards compliance guaranteed at
device level, hence greater immunity at system
level ESD protection of VBUS, when applicable,
allows ESD current flowing to ground when
ESD event occurs on data line Optimized rise and fall times for maximum data
integrity Consistent D+ / D- signal balance: Optimum capacitance matching tolerance
for ultralow intra-pair skew:
I/O to ground = 0.015 pF,
I/O to I/O = 0.007 pF Matching high bit rate DVI, HDMI, and
IEEE 1394 requirements Low PCB space occupation: 9 mm2 Low leakage current for longer operation of
battery powered devices Higher reliability offered by monolithic
integration
Complies with these standards IEC 61000-4-2 level 4: ±15 kV (air discharge) ±8 kV (contact discharge) MIL STD883G-Method 3015-7
Applications DVI ports up to 1.65 Gb/s HDMI ports up to 1.65 Gb/s IEEE 1394a, and b up to 1.6 Gb/s USB 2.0 ports up to 480 Mb/s (high speed),
backwards compatible with USB 1.1 low and
full speed Ethernet port: 10/100/1000 Mb/s SIM card protection Video line protection
DescriptionThe DVIULC6-4SC6 is a monolithic, application
specific discrete device dedicated to ESD
protection of high speed interfaces, such as DVI,
HDMI, IEEE 1394a, and b, USB 2.0, Ethernet
links and video lines.
Its ultralow line capacitance secures a high level
of signal integrity without compromise in
protecting sensitive chips against the most
stringently characterized ESD strikes.
Characteristics DVIULC6-4SC6 Doc ID 11599 Rev 4
1 Characteristics
Figure 1. Functional diagram
Table 1. Absolute ratings
Table 2. Electrical characteristics (Tamb = 25 °C)
DVIULC6-4SC6 CharacteristicsDoc ID 11599 Rev 4 3/12
Figure 2. Line capacitance versus line
voltage (typical values)
Figure 3. Line capacitance versus frequency
(typical values)
Figure 4. Relative variation of leakage
current versus junction
temperature (typical values)
Figure 5. Frequency response
Figure 6. Remaining voltage after the
DVIULC6-4SC6 during
positive ESD surge(1)
Figure 7. Remaining voltage after the
DVIULC6-4SC6 during
negative ESD surge(1) measurements were done with DVIULC-4SC6 in open circuit
Characteristics DVIULC6-4SC6 Doc ID 11599 Rev 4
Figure 8. Analog crosstalk results
DVIULC6-4SC6 Application examplesDoc ID 11599 Rev 4 5/12
2 Application examples
Figure 9. DVI/HDMI digital single link application
Figure 10. T1/E1/Ethernet protection
Technical information DVIULC6-4SC66/12 Doc ID 11599 Rev 4
3 Technical information
3.1 Surge protectionThe DVIULC6-4SC6 is particularly optimized to perform ESD surge protection based on the
rail to rail topology.
The clamping voltage VCL can be calculated as follows:
VCL+ = VBUS + VF, for positive surges
VCL- = - VF, for negative surges
with: VF = VT + Rd.Ip
VF = forward drop voltage, VT = forward drop threshold voltage)
Calculation exampleWe can assume that the value of the dynamic resistance of the clamping diode is typically:
Rd = 1.4 and VT = 1.2 V.
For an IEC 61000-4-2 surge Level 4 (Contact Discharge: Vg = 8 kV, Rg = 330 ),
VBUS = +5 V , and, in a first approximation, we assume that: Ip = Vg / Rg = 24 A.
We find:
VCL+ = +39 V
VCL- = -34 V
Note: The calculations do not take into account phenomena due to parasitic inductances.
3.2 Surge protection application exampleIf we consider that the connections from the pin VBUS to VCC and from GND to PCB GND
plane are two tracks 10 mm long and 0.5 mm wide, we can assume that the parasitic
inductances, LW of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs,
due to the rise time of this spike (tr = 1 ns), the voltage VCL has an extra value equal to
LW·dI/dt.
The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns for an IEC 61000-4-2 surge level 4 (contact
discharge Vg = 8 kV, Rg = 330
The over voltage due to the parasitic inductances is: LW.dI/dt = 6 x 24 = 144 V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the
clamping voltage will be:
VCL+ = +39 + 144 = 183 V
VCL- = -34 - 144 = -178 V
We can reduce as much as possible these phenomena with simple layout optimization.
This is the reason why some recommendations have to be followed (see Section 3.3: How
to ensure good ESD protection).