DVIULC6-2P6 Fast Delivery |IC PHOENIX CO.,LIMITED

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DVIULC6-2P6
Ultra Low capacitance 2 lines ESD protection
May 2008 Rev 1 1/17
DVIULC6-2x6
Ultra low capacitance ESD protection
Features 2-line ESD protection (at 15 kV air and contact
discharge, exceeds IEC 61000-4-2) Protects VBUS when applicable Ultra low capacitance: 0.6 pF at F = 825 MHz Fast response time compared with varistors Low leakage current: 0.5 µA max RoHS compliant
Benefits ESD standards compliance guaranteed at
device level, hence greater immunity at system
level ESD protection of VBUS when applicable. Large bandwidth to minimize impact on data
signal quality Consistent D+ / D- signal balance: Ultra low impact on intra- and inter-pair
skew Matching high bit rate DVI, and IEEE 1394
requirements Low PCB space consumption - 1.45 mm2
for µQFN Low leakage current for longer operation of
battery powered devices Higher reliability offered by monolithic
integration 500 µm pitch for µQFN 6 leads
Complies with these standards IEC 61000-4-2 level 4 15 kV air discharge 8 kV contact discharge MIL STD883G-Method 3015-7
Applications DVI ports up to 1.65 Gb/s IEEE 1394a, b, and c up to 3.2 Gb/s USB2.0 ports up to 480 Mb/s (high speed),
backwards compatible with USB1.1 low and full
speed Ethernet port: 10/100/1000 Mb/s SIM card protection Video line protection
Description
The DVIULC6-2x6 is a monolithic, application
specific discrete device dedicated to ESD
protection of high speed interfaces, such as DVI,
IEEE 1394a, b and c, USB2.0, Ethernet links and
video lines.
Its ultra low line capacitance secures a high level
of signal integrity without compromising in
protecting sensitive chips against the most
stringently characterized ESD strikes.
Characteristics DVIULC6-2x6
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1 Characteristics
Figure 1. Functional diagram

Table 1. Absolute ratings
Table 2. Electrical characteristics (Tamb = 25 °C)
DVIULC6-2x6 Characteristics
3/17

Figure 2. Line capacitance versus line
voltage (typical values)
Figure 3. Line capacitance versus frequency
(typical values) DVIULC6-2M6
Figure 4. Line capacitance versus frequency
(typical values) DVIULC6-2P6
Figure 5. Frequency response (typical
values) DVIULC6-2M6
Figure 6. Frequency response (typical
values) DVIULC6-2P6
Figure 7. Relative variation of leakage
current versus junction
temperature (typical values)
Characteristics DVIULC6-2x6
4/17

Figure 8. Eye diagram at 1.65 Gbps
amplitude 500 mV
PCB + DVIULC6-2M6
Figure 9. Eye diagram at 3.2 Gbps
amplitude 500 mV
PCB + DVIULC6-2M6
Figure 10. Eye diagram at 1.65 Gbps
amplitude 500 mV
PCB + DVIULC6-2P6
Figure 11. Eye diagram at 3.2 Gbps
amplitude 500 mV
PCB + DVIULC6-2P6
DVIULC6-2x6 Application examples
5/17
2 Application examples
Figure 12. DVI single link application
Figure 13. T1/E1/Ethernet protection
Application examples DVIULC6-2x6
6/17
2.1 PCB layout considerations
Figure 14. PCB layout example
Figure 15. TDR results for DVIULC6-2M6 with PCB layout example
DVIULC6-2x6 Technical information
7/17
3 Technical information
3.1 Surge protection
The DVIULC6-2x6 is particularly optimized to perform ESD surge protection based on the
rail to rail topology.
The clamping voltage VCL can be calculated as follows:
with: VF = VT + Rd.Ip
(VF forward drop voltage) / (VT forward drop threshold voltage)
and VTRANSIL = VBR + Rd_TRANSIL . IP
Calculation example
We assume that the value of the dynamic resistance of the clamping diode is typically:
Rd = 0.5 Ω and VT = 1.1 V.
We assume that the value of the dynamic resistance of the transil diode is typically
Rd_TRANSIL = 0.5 Ω and VBR = 6.1 V
For an IEC 61000-4-2 surge Level 4 (Contact Discharge: Vg= 8 kV , Rg= 330 Ω),
VBUS = +5 V , and, in first approximation, we assume that: Ip = Vg / Rg = 24 A.
We find:
Note: The calculations do not take into account phenomena due to parasitic inductances.
3.2 Surge protection application example
If we consider that the connections from the pin VBUS to VCC, from I/O to data line, and from
GND to PCB GND plane are two tracks 10 mm long and 0.5 mm wide, we can assume that
the parasitic inductances, LVBUS, LI/O, and LGND, of these tracks are about 6 nH. So when an
IEC 61000-4-2 surge occurs on the data line, due to the rise time of this spike (tr = 1 ns), the
voltage VCL has an extra value equal to LI/O.dI/dt + LGND.dI/dt.
The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns for an IEC 61000-4-2 surge level 4 (contact
discharge Vg = 8 kV, Rg = 330 Ω)
The over voltage due to the parasitic inductances is:
LI/O.dI/dt = LGND.dI/dt = 6 x 24 = 144 V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the
clamping voltage will be:
We can reduce as much as possible these phenomena with simple layout optimization.
VCL+ = VTRANSIL + VF for positive surges
VCL- = - VF for negative surges
VCL+ = +31.2 V
VCL- = -13.1 V
VCL+ = +31.2 + 144 +144 = 319.2 V
VCL- = -13.1 - 144 -144 = -301.1 V
Technical information DVIULC6-2x6
8/17
Figure 16. IESD behavior: parasitic phenomena due to unsuitable layout
Figure 17. ESD behavior - measurement conditions

Figure 18. Remaining voltage after the
DVIULC6-2M6 during
positive ESD surge
Figure 19. Remaining voltage after the
DVIULC6-2M6 during
negative ESD surge
DVIULC6-2x6 Technical information
9/17

Important
An important precaution to take is to put the protection device as close as possible to the
disturbance source (generally the connector).
3.3 Crosstalk behavior
Figure 22. Crosstalk phenomena
The crosstalk phenomena is due to the coupling between 2 lines. The coupling factor (β12 or 21 ) increases when the gap across lines decreases, particularly in silicon dice. In the
example above the expected signal on load RL2 is α2VG2 , in fact the real voltage at this point
has got an extra value β21VG1 . This part of the VG1 signal represents the effect of the
crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into
account when the drivers impose fast digital data or high frequency analog signals in the
disturbing line. The perturbed line will be more affected if it works with low voltage signal or
high load impedance (few kΩ).
Figure 20. Remaining voltage after the
DVIULC6-2P6 during
positive ESD surge
Figure 21. Remaining voltage after the
DVIULC6-26 during
negative ESD surge

Partno	Mfg	Dc	Qty	Available	Descript
DVIULC6-2P6 \|DVIULC62P6	ST	N/a	226000	avai	Ultra Low capacitance 2 lines ESD protection