DSM2190F4V-15K6 ,DSM (DIGITAL SIGNAL PROCESSOR SYSTEM MEMORY) FOR ANALOG DEVICES ADSP-2191 DSPS (3.3V SUPPLY)FEATURES SUMMARY■ Glueless Connection to DSP Figure 1. Packages– Easily add memory, logic, and I/O ..
DSP101KP ,DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS
DSP102JP ,DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS
DSP1A-DC6V , 1a 8A, 1a1b/2a 5A small polarized power relays
DSP1A-L-DC24V , 8 A MINIATURE POWER RELAY IN DS RELAY SERIES Latching types available
DSP1-DC12V , MINIATURE POWER RELAY IN DS RELAY SERIES
ED1402 ,NPN general purpose transistor
ED1402B ,NPN general purpose transistor
ED1402B ,NPN general purpose transistor
ED1402C ,NPN general purpose transistor
ED1402C ,NPN general purpose transistor
ED1402E ,NPN general purpose transistor
DSM2190F4V-15K6
DSM (DIGITAL SIGNAL PROCESSOR SYSTEM MEMORY) FOR ANALOG DEVICES ADSP-2191 DSPS (3.3V SUPPLY)
1/61September 2002
DSM2190F4VDSM (Digital Signal Processor System Memory)
For Analog Devices ADSP-2191 DSPs (3.3V Supply)
FEATURES SUMMARY Glueless Connection to DSP Easily add memory, logic, and I/O to the Exter-
nal Port of ADSP-2191 DSP
Dual Flash Memories Two independent Flash memory arrays for stor-
ing DSP code and data. DSP may access the
two arrays concurrently (read from one while
erasing or writing the other) 256K x 8 Main Flash memory divided into 8 sec-
tors (32KByte each) Ample storage for booting DSP code/data
upon reset and subsequent code swaps Large capacity for data recording 32K x 8 Secondary Flash memory divided into 4
sectors (8 KByte each). Multiple uses: Small sector size ideal for small data sets,
and calibration or configuration constants Store custom start-up code in one or more
sectors and configure DSP to run from exter-
nal memory upon reset (no boot) Concatenate Secondary Flash with Main
Flash for total of 288 KBytes Each Flash sector can be write protected. Built-in programmable address decoding logic
allows mapping individual Flash sectors to any
address boundary
Up to 16 Multifunction I/O Pins Increase total DSP system I/O capability I/O controlled by DSP software or PLD logic
General purpose PLD Over 3,000 Gates of PLD with 16 macro cells Use for peripheral glue logic to keypads, control
panel, displays, LCDs, and other devices Eliminate PLDs and external logic devices Create state machines, chip selects, simple
shifters and counters, clock dividers, delays Simple PSDsoft ExpressTM software...Free
Operating Range–VCC: 3.3V±10%; Temperature: –40o C to +85oC
Figure 1. Packages In-System Programming (ISP) with JTAG Program entire chip in 10-25 seconds with no in-
volvement of the DSP Links with ADSP-2191 JTAG debug port Eliminate sockets for pre-programmed memory
and logic devices ISP allows efficient manufacturing and product
testing supporting Just-In-Time inventory Use low-cost FlashLINKTM cable with PC
Content Security Programmable Security Bit blocks access of de-
vice programmers and readers
Zero-Power Technology As low as 25μA standby current
Packaging 52-pin PQFP or 52-pin PLCC
Flash Memory Speed, Endurance, Retention 150 ns, 100K cycles, 15 year retention
DSM2190F4
TABLE OF CONTENTS
Summary Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6DSP Address/Data/Control Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Main Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Secondary Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Programmable Logic (PLDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Runtime Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Memory Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
JTAG ISP Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Security and NVM Sector Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Typical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Typical Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Specifying the Memory Map with PSDsoft ExpressTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Runtime control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Detailed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Flash Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Instruction Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Reading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Erasing Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Flash Memory Sector Protect.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DSM Security Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Decode PLD (DPLD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3/61
DSM2190F4
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26DSP Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Port B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Port C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Port D – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37PLD Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Power On Reset, Warm Reset, Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Programming In-Circuit using JTAG ISP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
AC/DC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42Table: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Table: Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table: DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table: CPLD Combinatorial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table: CPLD Macrocell Synchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table: CPLD Macrocell Asynchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table: Input Macrocell Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table: Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table: Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table: Flash Memory Program, Write and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table: Reset (Reset) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table: ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55Table: PLCC52 - 52 lead Plastic Leaded Chip Carrier, rectangular . . . . . . . . . . . . . . . . . . . . . . . .55
Table: Assignments – PLCC52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table: PQFP52 - 52 lead Plastic Quad Flatpack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table: Pin Assignments – PQFP52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Table: Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
DSM2190F4
SUMMARY DESCRIPTIONThe DSM2190F4 is a system memory device for
use with the Analog Devices ADSP-2191 DSP.
DSM means Digital signal processor System
Memory. A DSM device brings In-System Pro-
grammable (ISP) Flash memory, parameter stor-
age, programmable logic, and additional I/O to
DSP systems. The result is a simple and flexible
two-chip solution for DSP designs. DSM devices
provide the flexibility of Flash memory and smart
JTAG programming techniques for both manufac-
turing and the field. On-chip integrated memory
decode logic makes it easy to map dual banks of
Flash memory to the ADSP-2191 in a variety of
ways for bootloading, code execution, data re-
cording, code swapping, and parameter storage.
JTAG ISP reduces development time, simplifies
manufacturing flow, and lowers the cost of field up-
grades. The JTAG ISP interface eliminates the
need for sockets and pre-programmed memory
and logic devices. For manufacturing, end prod-
ucts may be assembled with a blank DSM device
soldered to the circuit board and programmed at
the end of the manufacturing line in 10 to 25 sec-
onds with no involvement of the DSP. This allows
efficient means to test product and manage inven-
tory by rapidly programming test code, then appli-
cation code as determined by inventory
requirements (Just-In Time inventory). Additional-
ly, JTAG ISP reduces development time by turning
fast iterations of DSP code in the lab. Code up-
dates in the field require no disassembly of prod-
uct. The FlashLINKTM JTAG programming cable
costs $59 USD and plugs into any PC or note-
book parallel port.
In addition to ISP Flash memory, DSM devices
add programmable logic (PLD) and up to 16 con-
figurable I/O pins to the DSP system. The state of
each I/O pin can be driven by DSP software or
PLD logic. PLD and I/O configuration are program-
mable by JTAG ISP, just like the Flash memory.
The PLD consists of more than 3000 gates and
has 16 macro cell registers. Common uses for the
PLD include chip selects for external devices,
state-machines, simple shifters and counters, key-
pad and control panel interfaces, clock dividers,
handshake delay, multiplexers, etc. This elimi-
nates the need for small external PLDs and logic
devices. Configuration of PLD, I/O, and Flash
memory mapping are easily entered in a point-
and-click environment using the software develop-
ment tool, PSDsoft ExpressTM. This software is
available at no charge from /psm.
Figure 2. System Block Diagram, Two-Chip Solution
5/61
DSM2190F4The two-chip combination of a DSP and a DSM
device is ideal for systems which have limitations
on size, EMI levels, and power consumption. DSM
memory and logic are “zero-power”, meaning they
automatically go to standby between memory ac-
cesses or logic input changes, producing low ac-
tive and standby current consumption, which is
ideal for battery powered products.
A programmable security bit in the DSM protects
its contents from unauthorized viewing and copy-
ing. When set, the security bit will block access of
programming devices (JTAG or others) to the
DSM Flash memories and PLD configuration. The
only way to defeat the security bit is to erase the
entire DSM device, after which the device is blank
and may be used again. The DSP will always have
access to Flash memory contents through the 8-bit
data port even while the security bit is set.
Table 1. DSM2190F4V DSP Memory System Devices
Table 2. Compatible Analog Devices DSP
Figure 3. PLCC Connections Figure 4. PQFP Connections
DSM2190F4
ARCHITECTURAL OVERVIEW Major functional blocks are shown in Figure 5.
DSP Address/Data/Control InterfaceThese DSP signals attach directly to the DSM for
a glueless connection. An 8-bit data connection is
formed and all 22 DSP address lines can be de-
coded as well as DSP memory strobes; BMS,
IOMS, and MSx. There are many different ways the
DSM2190F4 can be configured and used depend-
ing on system requirements. One convenient way
is to combine the function of the MSx signals into
the BMS signal. Doing this allows the DSP core to
access DSM memory at runtime even after the
boot process is complete using only the BMS sig-
nal. Combining MSx and BMS consumes less I/O
pin(s) on the DMS device. See Analog Devices
ADSP-2191 DSP Hardware Reference Manual,
Chapter 7, Code Example: BMS Runtime Access.
Alternatively, any of the MSx signals may also be
used to decode any of the sectors of DSM Main
Flash or Secondary flash memories.
Main Flash MemoryThe 2M bit (256K x 8) Flash memory is divided into
eight equally-sized 32K byte sectors that are indi-
vidually selectable through the Decode PLD. Each
Flash memory sector can be located at any ad-
dress as defined by the user with PSDsoft Ex-
press. DSP code and data is easily placed in flash
memory using the PSDsoft Express software de-
velopment tool.
Secondary Flash MemoryThe 256K bit (32K x 8) Flash memory is divided
into eight equally-sized 8K byte sectors that are in-
dividually selectable through the Decode PLD.
Each Flash memory sector can be located at any
address as defined by the user with PSDsoft Ex-
press. DSP code and data can also be placed
Secondary Flash memory using the PSDsoft Ex-
press development tool.
Secondary flash memory is good for storing data
because of its small sectors. Additionally, software
EEPROM emulation techniques can be used for
small data sets that change frequently on a byte-
by-byte basis.
Secondary flash may also be used to store custom
start-up code for applications that do not “boot” us-
ing DMA, but instead start executing code from ex-
ternal memory upon reset. Storing code here can
keep the entire Main Flash free of initialization
code for clean software partitioning. If only one or
more 8K byte sectors are needed for start-up
code, the remaining sectors of Secondary Flash
may be used for data storage.
Secondary Flash may also be used as an exten-
sion to Main Flash memory producing a total of
288K bytes
Miscellaneous: Main and Secondary Flash memo-
ries are totally independent, allowing concurrent
operation if needed. The DSP can read from one
memory while erasing or programming the other.
The DSP can erase Flash memories by individual
sectors or the entire Flash memory array may be
erased at one time. Each sector in either Flash
memory may be individually write protected, block-
ing any writes from the DSP (good for boot and
start-up code protection). The Flash memories au-
tomatically go to standby between DSP read or
write accesses to conserve power. Maximum ac-
cess times include sector decoding time. Maxi-
mum erase cycles is 100K and data retention is 15
years minimum. Flash memory, as well as the en-
tire DSM device may be programmed with the
JTAG ISP interface with no DSP involvement.
Programmable Logic (PLDs) The DSM family contains two PLDS that may op-
tionally run in Turbo or Non-Turbo mode. PLDs op-
erate faster (less propagation delay) while in
Turbo mode but consume more power than Non-
Turbo mode. Non-Turbo mode allows the PLDs to
automatically go to standby when no inputs are
change to conserve power. The Turbo mode set-
ting is controlled at runtime by DSP software.
Decode PLD (DPLD). This is programmable log-
ic used to select one of the eight individual Main
Flash memory segments, one of four individual
Secondary Flash memory segments, or the group
of control registers within the DSM device. The
DPLD can also optionally drive external chip select
signals on Port D pins. DPLD input signals include:
DSP address and control signals, Page Register
outputs, DSM Port Pins, CPLD logic feedback.
Complex PLD (CPLD). This programmable logic
is used to create both combinatorial and sequen-
tial general purpose logic. The CPLD contains 16
Output Macrocells (OMCs) and 16 Input Macro-
cells (IMCs). PSD Macrocell registers are unique
in that that have direct connection to the DSP data
bus allowing them to be loaded and read directly
by the DSP at runtime. This direct access is good
for making small peripheral devices (shifters,
counters, state machines, etc.) that are accessed
directly by the DSP with little overhead. DPLD in-
puts include DSP address and control signals,
Page Register outputs, DSM Port Pins, and CPLD
feedback.
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DSM2190F4
Figure 5. Block DiagramOMCs: The general structure of the CPLD is simi-
lar in nature to a 22V10 PLD device with the famil-
iar sum-of-products (AND-OR) construct. True
and compliment versions of 64 input signals are
available to a large AND array. AND array outputs
feed into a multiple product-term OR gate within
each OMC (up to 10 product-terms for each
OMC). Logic output of the OR gate can be passed
on as combinatorial logic or combined with a flip-
flop within in each OMC to realize sequential logic.
OMCs can be used as a buried nodes with feed-
back to the AND array or OMC output can be rout-
ed to pins on Port B or PortC.
IMCs: Inputs from pins on Port B or Port C are
routed to IMCs for conditioning (clocking or latch-
ing) as they enter the chip, which is good for sam-
pling and debouncing inputs. Alternatively, IMCs
can pass Port input signals directly to PLD inputs
without clocking or latching. The DSP may read
the IMCs at any time.
Runtime Control RegistersA block of 256 bytes is decoded inside the DSM
device as DSM control and status registers. 27
registers are used in the block of 256 locations to
control the output state of I/O pins, to read I/O
pins, to control power management, to read/write
macrocells, and other functions at runtime. See
Table 4 for description. The base address of these
256 locations is referred to in this data sheet as
csiop (Chip Select I/O Port). Individual registers
within this block are accessed with an offset from
the base address. The DSP accesses csiop regis-
ters using I/O memory with the IOMS strobe. csiop
registers are accessed as bytes.
Memory Page RegisterThis 8-bit register can be loaded and read by the
DSP at runtime as one of the csiop registers. Its
outputs feed directly into the PLDs. The page reg-
ister can be used for special memory mapping re-
quirements and also for general logic.
DSM2190F4
I/O PortsThe DSM has 19 individually configurable I/O pins
distributed over the three ports (Ports B, C, and D).
Each I/O pin can be individually configured for dif-
ferent functions such as standard MCU I/O ports
or PLD I/O on a pin by pin basis. (MCU I/O means
that for each pin, its output state can be controlled
or its input value can be read by the DSP at runt-
ime using the csiop registers like an MCU would
do.)
Port C hosts the JTAG ISP signals. Since JTAG-
ISP does not occur frequently during the life of a
product, those Port C pins are under-utilized. In
applications that need every I/O pin, JTAG signals
can be multiplexed with general I/O signals to use
them for I/O when not performing ISP. See section
titled “Programming In-Circuit using JTAG ISP” on
page 40 for muxing JTAG pins on Port C, and Ap-
plication Note AN1153.
The static configuration of all Port pins is defined
with the PSDsoft ExpressTM software develop-
ment tool. The dynamic action of the Ports pins is
controlled by DSP runtime software.
JTAG ISP PortIn-System Programming (ISP) can be performed
through the JTAG signals on Port C. This serial in-
terface allows programming of the entire DSM de-
vice or subsections (that is, only Flash memory but
not the PLDs) without the participation of the DSP.
A blank DSM device soldered to a circuit board
can be completely programmed in 10 to 25 sec-
onds. The basic JTAG signals; TMS, TCK, TDI,
and TDO form the IEEE-1149.1 interface. The
DSM device does not implement the IEEE-1149.1
Boundary Scan functions. The DSM uses the
JTAG interface for ISP only. However, the DSM
device can reside in a standard JTAG chain with
other JTAG devices (including the ADSP-2191)
and it will remain in BYPASS mode while other de-
vices perform Boundary Scan.
ISP programming time can be reduced as much as
30% by using two more signals on Port C, TSTAT
and TERR in addition to TMS, TCK, TDI and TDO.
The FlashLINKTM JTAG programming cable is
available from STMicroelectronics for $59USD
and PSDsoft Express software is available at no
charge from /psm. That is all that is
needed to program a DSM device using the paral-
lel port on any PC or note-book. See section titled
“Programming In-Circuit using JTAG ISP” on page
Power Management
The DSM has bits in csiop control registers that
are configured at run-time by the DSP to reduce
power consumption of the CPLD. The Turbo bit in
the PMMR0 register can be set to logic 1 and the
CPLD will go to Non-Turbo mode, meaning it will
latch its outputs and go to sleep until the next tran-
sition on its inputs. There is a slight penalty in PLD
performance (longer propagation delay), but sig-
nificant power savings are realized.
Additionally, bits in two csiop registers can be set
by the DSP to selectively block signals from enter-
ing the CPLD which reduces power consumption.
See section titled “Power Management” on page
Security and NVM Sector Protection
A programmable security bit in the DSM protects
its contents from unauthorized viewing and copy-
ing. When set, the security bit will block access of
programming devices (JTAG or others) to the
DSM Flash memory and PLD configuration. The
only way to defeat the security bit is to erase the
entire DSM device, after which the device is blank
and may be used again.
Additionally, the contents of each individual Flash
memory sector can be write protected (sector pro-
tection) by configuration with PSDsoft ExpressTM.
This is typically used to protect DSP boot code
from being corrupted by inadvertent writes to
Flash memory from the DSP.
Pin AssignmentsPin assignment are shown for the 52-pin PLCC
package in Figure 3, and the 52-pin PQFP pack-
age in Figure 4.
9/61
DSM2190F4
Table 3. Pin Description
DSM2190F4
TYPICAL CONNECTIONSFigure 6 shows a typical connection scheme.
Many connection possibilities exist since many
DSM pins are multipurpose. This scheme illus-
trates the use of a combined function BSM signal
(functions as BMS and MSx), and many I/O pins. It
also illustrates how to chain the DSM and DSP de-
vices together on the JTAG bus. The JTAG con-
nector definition depends on development and
production environment requirements. A specially
defined connector can be devised to combine the
signals of the FlashLINK and the Analog Devices
emulator. Alternatively, two separate JTAG con-
nectors can be used, one matching the pinout of
FlashLINK and the other matching the emulator pi-
nout.
Keep in mind that signals BMS, IOMS, MSx,
ADDR16, ADDR17, ADDR18 can be connected to
any DSM pin that is a PLD input. I/O pins on Port
B and Port C are more capable (more PLD func-
tions) than Port D pins. It is recommended to use
Port D pins primarily for decode inputs first, leav-
ing pins on Port B and Port C available for general
logic. Figure 6 illustrates a common way to make
connections.
Following are connection options to consider:
Port C JTAG: Figure 6 shows four JTAG signals
(TMS, TCK, TDI, TDO) connected to the DSM. Al-
ternatively, using six-pin JTAG (two more signals,
TSTAT and TERR) can reduce ISP time by as
much as 30% compared to four-pin JTAG. Other
JTAG options include multiplexing JTAG pins with
general I/O (see “Programming In-Circuit using
JTAG ISP” on page 40 and Application Note
AN1153), or not using JTAG at all. If no JTAG is
used, the DSM device has to be programmed on a
conventional programmer before it is installed on
the circuit board. Using no JTAG makes more
DSM I/O available.
Pins PC2 and PD2. If not all 288K address loca-
tions need to be decoded in the DSM, then
ADDR18 on pin PD2 is not needed. In this case,
the IOMS signal can be connected to pin PD2, free-
ing pin PC2 for general I/O usage.
11/61
DSM2190F4
DSM2190F4
TYPICAL MEMORY MAPThere many different ways to place (or map) the
addresses of DSM memory and I/O depending on
system requirements. The DPLD allows complete
mapping flexibility. Figure 7 shows one possible
system memory map. In this case, the DSP will
bootload (via DMA) the contents of Main Flash
memory upon reset. The Secondary Flash memo-
ry can be used for parameter storage or additional
code storage. BMS and MSx are configured in the
DSP to be combined into the BMS signal, allowing
the DSP to access both Flash memories at runt-
ime (after DMA boot). The DSP may execute code
directly from the DSM and well as erase and write
new code or data to DSM Flash.
The nomenclature fs0..fs7 are designators for the
individual sectors of Main Flash memory, 32K
bytes each. csboot0..csboot3 are designators for
the individual Secondary Flash memory seg-
ments, 8K bytes each. csiop designates the DSM
control register block.
The designer may easily specify memory mapping
in a point-and-click software environment using
PSDsoft ExpressTM.
13/61
DSM2190F4
DSM2190F4
SPECIFYING THE MEMORY MAP WITH PSDSOFT EXPRESSTMThe memory map shown in Figure 7 can be easily
implemented using PSDsoft ExpressTM in a point-
and-click environment. PSDsoft ExpressTM will
generate Hardware Definition Language (HDL)
statements of the ABEL language. Figure 8 shows
the resulting equations generated by PSDsoft Ex-
pressTM.
Specifying these equations using PSDsoft Ex-
pressTM is very simple. Figure 9 shows how to
specify the equation for the 32K Byte Flash mem-
ory segment, fs2. Notice fs2 is qualified with the
signals BMS. This specification process is repeat-
ed for all other Flash memory segments, the csiop
register block, and any external chip select signals
that may be needed (ADC, etc.).
15/61
DSM2190F4
RUNTIME CONTROL REGISTER DEFINITIONThere are up to 256 addresses decoded inside the
DSM device for control and status information. 27
of these locations contain registers that the DSP
can access at runtime. The base address of this
block of 256 locations is referred to in this manual
as csiop (Chip Select I/O Port). Table 4 lists the 27
registers and their offsets (in hexadecimal) from
the csiop base address needed to access individ-
ual DSM control and status registers. The DSP will
access these registers in I/O memory space using
its IOMS strobe. These registers are accesses in
bytes, so the DSP should ignore the upper byte of
its 16-bit I/O access.
Note1: All csiop registers are cleared to logic 0 at
reset.
Note2: Do not write to unused locations within the
csiop block of 256 registers. They should remain
logic zero.
Table 4. CSIOP Registers and their Offsets (in hexadecimal)
DSM2190F4
DETAILED OPERATIONFigure 5 shows major functional areas of the de-
vice: Flash Memories PLDs (DPLD, CPLD, Page Register) DSP Bus Interface (Address, Data, Control) I/O Ports Runtime Control Registers JTAG ISP Interface
The following describes these functions in more
detail.
Flash MemoriesThe Main Flash memory array is divided into eight
equal 32K byte sectors. The Secondary Flash
memory array is divided into four equal 8K byte
sectors. Each sector is selected by the DPLD can
be separately protected from program and erase
cycles. This configuration is specified by using PS-
Dsoft ExpressTM.
Memory Sector Select Signals. The DPLD gen-
erates the Select signals for all the internal memo-
ry blocks (see Figure 14). Each of the twelve
sectors of the Flash memories has a select signal
(FS0-FS7, or CSBOOT0-CSBOOT3) which con-
tains up to three product terms. Having three prod-
uct terms for each select signal allows a given
sector to be mapped into multiple areas of system
memory if needed.
Ready/Busy (PC3). This signal can be used to
output the Ready/Busy status of the device. The
output on Ready/Busy is a 0 (Busy) when either
Flash memory array is being written, or when ei-
ther Flash memory array is being erased. The out-
put is a 1 (Ready) when no Write or Erase cycle is
in progress. This signal may be polled by the DSP
or used as a DSP interrupt to indicate when an
erase or program cycle is complete.
Memory Operation. The Flash memories are ac-
cessed through the DSP Address, Data, and Con-
trol Bus Interface.
DSPs and MCUs cannot write to Flash memory as
it would an SRAM device. Flash memory must first
be “unlocked” with a special sequence of byte
write operations to invoke an internal algorithm,
then a single data byte is written to the Flash mem-
ory array, then programming status is checked by
a byte read operation or by checking the Ready/
Busy pin (PC3). Table 5 lists all of the special in-
struction sequences to program (write) data to the
Flash memory arrays, erase the arrays, and check
for different types of status from the arrays. These
instruction sequences are different combinations
of individual byte write and byte read operations.
IMPORTANT: The DSP may not read and execute
code from the same Flash memory array for which
it is directing an instruction sequence. Or more
simply stated, the DSP may not read code the
same Flash array that is writing or erasing. In-
stead, the DSP must execute code from an alter-
nate memory (like its own internal SRAM or a
different Flash array) while sending instructions to
a given Flash array. Since the two Flash memory
arrays inside the DSM device are completely inde-
pendent, the DSP may read code from one array
while sending instructions to the other.
After a Flash memory array is programmed (writ-
ten) it will go to “Read Array” mode, then the DSP
can read from Flash memory just as if would from
any 8-bit ROM or SRAM device.
17/61
DSM2190F4
Table 5. Instruction Sequences 1,2,3,4Note:1. All values are in hexadecimal, X = Don’t Care A desired internal Flash memory sector select signal (FS0 - FS7 or CSBOOT0 - CSBOOT3) must be active for each write or read
cycle. Only one of these sector select signals will be active at any given time depending on the address presented by the DSP and
the memory mapping defined in PSDsoft Express. FS0 - FS7 and CSBOOT0-CSBOOT3 are active high logic internally. DSP addresses A18 through A12 are Don’t Care during the instruction sequence decoding. Only address bits A11-A0 are used
during Flash memory instruction sequence decoding bus cycles. The individual sector select signal (FS0 - FS7 or CSBOOT0-
CSBOOT3) which is active during the instruction sequences determines the complete address. For write operations, addresses are latched on the falling edge of Write Strobe (WR, CNTL0), Data is latched on the rising edge of
Write Strobe (WR, CNTL0) No Unlock or Instruction cycles are required when the device is in the Read Array mode. Operation is like reading a ROM device. The Reset Flash instruction is required to return to the normal Read Array mode if the Error Flag (DQ5) bit goes High, or after read-
ing the Flash Identifier or after reading the Sector Protection Status. The DSP cannot invoke this instruction sequence while executing code from the same Flash memory as that for which the instruc-
tion sequence is intended. The DSP must fetch, for example, the code from the DSP SRAM when reading the Flash memory Iden-
tifier or Sector Protection Status. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1,A0)=(1,0) Directing this command to any individual active Flash memory segment (FS0 - FS7) will invoke the bulk erase of all eight Flash
memory sectors.
10. DSP writes command sequence to initial segment to be erased, then writes the byte 30h to additional sectors to be erased. The
byte 30h must be addressed to one of the other Flash memory segments (FS0 - FS7) for each additional segment (write 30h to any
address within a desired sector). No more than 80uS can elapse between subsequent additional sector erase commands.
11. The system may perform Read and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protect Status,
when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction sequence is valid only during a Sector Erase cycle.
12. The Resume Sector Erase instruction sequence is valid only during the Suspend Sector Erase mode.
DSM2190F4
Instruction SequencesAn instruction sequence consists of a sequence of
specific write or read operations. Each byte written
to the device is received and sequentially decoded
and not executed as a standard write operation to
the memory array. The instruction sequence is ex-
ecuted when the correct number of bytes are prop-
erly received and the time between two
consecutive bytes is shorter than the time-out pe-
riod. Some instruction sequences are structured to
include read operations after the initial write oper-
ations.
The instruction sequence must be followed exact-
ly. Any invalid combination of instruction bytes or
time-out between two consecutive bytes while ad-
dressing Flash memory resets the device logic into
Read Array mode (Flash memory is read like a
ROM device). The device supports the instruction
sequences summarized in Table 5:
Flash memory: Erase memory by chip or sector Suspend or resume sector erase Program a Byte Reset to Read Array mode Read primary Flash Identifier value Read Sector Protection Status
These instruction sequences are detailed in Table
5. For efficient decoding of the instruction se-
quences, the first two bytes of an instruction se-
quence are the coded cycles and are followed by
an instruction byte or confirmation byte. The coded
cycles consist of writing the data AAh to address
XX555h during the first cycle and data 55h to ad-
dress XXAAAh during the second cycle. Address
signals A18-A12 are Don’t Care during the instruc-
tion sequence Write cycles. However, the appro-
priate internal Sector Select (FS0-FS7 or
CSBOOT0-CSBOOT3) must be selected internal-
ly (active, which is logic 1).
Reading Flash MemoryUnder typical conditions, the DSP may read the
Flash memory using read operations just as it
would a ROM or RAM device. Alternately, the DSP
may use read operations to obtain status informa-
tion about a Program or Erase cycle that is cur-
rently in progress. Lastly, the DSP may use
instruction sequences to read special data from
these memory blocks. The following sections de-
scribe these read instruction sequences.
Read Memory Contents. Flash memory is
placed in the Read Array mode after Power-up,
chip reset, or a Reset Flash memory instruction
sequence (see Table 5). The DSP can read the
memory contents of the Flash memory by using
read operations any time the read operation is not
part of an instruction sequence.
Read Main Flash Identifier. The Main Flash
memory identifier is read with an instruction se-
quence composed of 4 operations: 3 specific write
operations and a read operation (see Table 5).
During the read operation, address bits A6, A1,
and A0 must be 0,0,1, respectively, and the appro-
priate internal Sector Select (FS0-FS7) must be
active. The identifier is 0xE7. Not Applicable to
Secondary Flash.
Read Memory Sector Protection Status. The
Flash memory Sector Protection Status is read
with an instruction sequence composed of 4 oper-
ations: 3 specific write operations and a read oper-
ation (see Table 5). During the read operation,
address bits A6, A1, and A0 must be 0,1,0, re-
spectively, while internal Sector Select (FS0-FS7
or CSBOOT0-CSBOOT3) designates the Flash
memory sector whose protection has to be veri-
fied. The read operation produces 01h if the Flash
memory sector is protected, or 00h if the sector is
not protected.
The sector protection status can also be read by
the DSP accessing the Flash memory Protection
registers in csiop space. See the section entitled
“Flash Memory Sector Protect” for register defini-
tions.
Table 6. Status Bit DefinitionNote:1. X = Not guaranteed value, can be read either 1 or 0. DQ7-DQ0 represent the Data Bus bits, D7-D0.
Reading the Erase/Program Status Bits. The
device provides several status bits to be used by
the DSP to confirm the completion of an Erase or
Program cycle of Flash memory. These status bits
minimize the time that the DSP spends performing
these tasks and are defined in Table 6. The status
bits can be read as many times as needed.
19/61
DSM2190F4For Flash memory, the DSP can perform a read
operation to obtain these status bits while an
Erase or Program instruction sequence is being
executed by the embedded algorithm. See the
section entitled “Programming Flash Memory”, on
page 19, for details.
Data Polling Flag (DQ7). When erasing or pro-
gramming in Flash memory, the Data Polling Flag
(DQ7) bit outputs the complement of the bit being
entered for programming/writing on the Data Poll-
ing Flag (DQ7) bit. Once the Program instruction
sequence or the write operation is completed, the
true logic value is read on the Data Polling Flag
(DQ7) bit (in a read operation).
Flash memory instruction features. Data Polling is effective after the fourth Write
pulse (for a Program instruction sequence) or
after the sixth Write pulse (for an Erase
instruction sequence). It must be performed at
the address being programmed or at an address
within the Flash memory sector being erased. During an Erase cycle, the Data Polling Flag
(DQ7) bit outputs a 0. After completion of the
cycle, the Data Polling Flag (DQ7) bit outputs
the last bit programmed (it is a 1 after erasing). If the byte to be programmed is in a protected
Flash memory sector, the instruction sequence
is ignored. If all the Flash memory sectors to be erased are
protected, the Data Polling Flag (DQ7) bit is
reset to 0 for about 100 μs, and then returns to
the previous addressed byte. No erasure is
performed.
Toggle Flag (DQ6). The device offers another
way for determining when the Flash memory Pro-
gram cycle is completed. During the internal write
operation and when the Sector Select FS0-FS7 (or
CSBOOT0-CSBOOT3) is true, the Toggle Flag
(DQ6) bit toggles from 0 to 1 and 1 to 0 on subse-
quent attempts to read any byte of the memory.
When the internal cycle is complete, the toggling
stops and the data read on the Data Bus D0-7 is
the addressed memory byte. The device is now
accessible for a new read or write operation. The
cycle is finished when two successive reads yield
the same output data. Flash memory specific fea-
tures: The Toggle Flag (DQ6) bit is effective after the
fourth write operation (for a Program instruction
sequence) or after the sixth write operation (for
an Erase instruction sequence). If the byte to be programmed belongs to a
protected Flash memory sector, the instruction
sequence is ignored. If all the Flash memory sectors selected for
erasure are protected, the Toggle Flag (DQ6) bit
toggles to 0 for about 100 μs and then returns to
the previous addressed byte.
Error Flag (DQ5). During a normal Program or
Erase cycle, the Error Flag (DQ5) bit is to 0. This
bit is set to 1 when there is a failure during Flash
memory Byte Program, Sector Erase, or Bulk
Erase cycle.
In the case of Flash memory programming, the Er-
ror Flag (DQ5) bit indicates the attempt to program
a Flash memory bit from the programmed state, 0,
to the erased state, 1, which is not valid. The Error
Flag (DQ5) bit may also indicate a Time-out condi-
tion while attempting to program a byte.
In case of an error in a Flash memory Sector Erase
or Byte Program cycle, the Flash memory sector in
which the error occurred or to which the pro-
grammed byte belongs must no longer be used.
Other Flash memory sectors may still be used.
The Error Flag (DQ5) bit is reset after a Reset
Flash instruction sequence.
Erase Time-out Flag (DQ3). The Erase Time-
out Flag (DQ3) bit reflects the time-out period al-
lowed between two consecutive Sector Erase in-
struction sequence bytes. The Erase Time-out
Flag (DQ3) bit is reset to 0 after a Sector Erase cy-
cle for a time period of 100 μs + 20% unless an ad-
ditional Sector Erase instruction sequence is
decoded. After this time period, or when the addi-
tional Sector Erase instruction sequence is decod-
ed, the Erase Time-out Flag (DQ3) bit is set to 1.
Programming Flash MemoryWhen a byte of Flash memory is programmed, in-
dividual bits are programmed to logic 0. You can-
not program a bit in Flash memory to a logic 1
once it has been programmed to a logic 0. A bit
must be erased to logic 1, and programmed to log-
ic 0. That means Flash memory must be erased
prior to being programmed. A byte of Flash mem-
ory is erased to all 1s (FFh). The DSP may erase
the entire Flash memory array all at once or indi-
vidual sector-by-sector, but not byte-by-byte.
However, the DSP may program Flash memory
byte-by-byte.
The Flash memory requires the DSP to send an in-
struction sequence to program a byte or to erase
sectors (see Table 5).
Once the DSP issues a Flash memory Program or
Erase instruction sequence, it must check for the
status bits for completion. The embedded algo-
rithms that are invoked inside the device provide
several ways give status to the DSP. Status may
DSM2190F4be checked using any of three methods: Data Poll-
ing, Data Toggle, or Ready/Busy (pin PC3).
Data Polling. Polling on the Data Polling Flag
(DQ7) bit is a method of checking whether a Pro-
gram or Erase cycle is in progress or has complet-
ed. Figure 10 shows the Data Polling algorithm.
When the DSP issues a Program instruction se-
quence, the embedded algorithm within the device
begins. The DSP then reads the location of the
byte to be programmed in Flash memory to check
status. The Data Polling Flag (DQ7) bit of this lo-
cation becomes the compliment of bit 7 of the orig-
inal data byte to be programmed. The DSP
continues to poll this location, comparing the Data
Polling Flag (DQ7) bit and monitoring the Error
Flag (DQ5) bit. When the Data Polling Flag (DQ7)
bit matches bit7 of the original data, and the Error
Flag (DQ5) bit remains 0, then the embedded al-
gorithm is complete. If the Error Flag (DQ5) bit is
1, the DSP should test the Data Polling Flag (DQ7)
bit again since the Data Polling Flag (DQ7) bit may
have changed simultaneously with the Error Flag
(DQ5) bit (see Figure 10).
The Error Flag (DQ5) bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte or if the DSP at-
tempted to program a 1 to a bit that was not erased
(not erased is logic 0).
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
byte that was written to the Flash memory with the
byte that was intended to be written.
When using the Data Polling method during an
Erase cycle, Figure 10 still applies. However, the
Data Polling Flag (DQ7) bit is 0 until the Erase cy-
cle is complete. A 1 on the Error Flag (DQ5) bit in-
dicates a time-out condition on the Erase cycle, a
0 indicates no error. The DSP can read any loca-
tion within the sector being erased to get the Data
Polling Flag (DQ7) bit and the Error Flag (DQ5) bit.
PSDsoft Express generates ANSI C code func-
tions which implement these Data Polling algo-
rithms.
Figure 10. Data Polling Flowchart
Data Toggle. Checking the Toggle Flag (DQ6) bit
is a method of determining whether a Program or
Erase cycle is in progress or has completed. Fig-
ure 11 shows the Data Toggle algorithm.
When the DSP issues a Program instruction se-
quence, the embedded algorithm within the device
begins. The DSP then reads the location of the
byte to be programmed in Flash memory to check
status. The Toggle Flag (DQ6) bit of this location
toggles each time the DSP reads this location until
the embedded algorithm is complete. The DSP
continues to read this location, checking the Tog-
gle Flag (DQ6) bit and monitoring the Error Flag
(DQ5) bit. When the Toggle Flag (DQ6) bit stops
toggling (two consecutive reads yield the same
value), and the Error Flag (DQ5) bit remains 0,
then the embedded algorithm is complete. If the
Error Flag (DQ5) bit is 1, the DSP should test the
Toggle Flag (DQ6) bit again, since the Toggle Flag
(DQ6) bit may have changed simultaneously with
the Error Flag (DQ5) bit (see Figure 11).
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DSM2190F4
Figure 11. Data Toggle FlowchartThe Error Flag (DQ5) bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte, or if the DSP at-
tempted to program a 1 to a bit that was not erased
(not erased is logic 0).
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
byte that was written to Flash memory with the
byte that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 11 still applies. the Toggle
Flag (DQ6) bit toggles until the Erase cycle is com-
plete. A 1 on the Error Flag (DQ5) bit indicates a
time-out condition on the Erase cycle, a 0 indi-
cates no error. The DSP can read any location
within the sector being erased to get the Toggle
Flag (DQ6) bit and the Error Flag (DQ5) bit.
PSDsoft Express generates ANSI C code func-
tions which implement these Data Toggling algo-
rithms.
Erasing Flash Memory
Flash Bulk Erase. The Flash Bulk Erase instruc-
tion sequence uses six write operations followed
by a read operation of the status register, as de-
scribed in Table 5. If any byte of the Bulk Erase in-
struction sequence is wrong, the Bulk Erase
instruction sequence aborts and the device is re-
set to the Read Flash memory status. The Bulk
Erase command may be addresses to any one in-
dividual valid Flash memory segment (FS0-FS7 or
CSBOOT0-CSBOOT3) and the entire array (all
segments in one array) will be erased.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag (DQ5) bit, the
Toggle Flag (DQ6) bit, and the Data Polling Flag
(DQ7) bit, as detailed in the section entitled “Pro-
gramming Flash Memory”, on page 19. The Error
Flag (DQ5) bit returns a 1 if there has been an
Erase Failure (maximum number of Erase cycles
have been executed).
It is not necessary to program the memory with
00h because the device automatically does this
before erasing to 0FFh.
During execution of the Bulk Erase instruction se-
quence, the Flash memory does not accept any in-
struction sequences.
The address provided with the Flash Bulk Erase
command sequence (Table 5) may select any one
of the eight internal Flash memory Sector Select
signals FS0 - FS7 or one of the four signals
CSBOOT0-CSBOOT3. An erase of that entire
Flash memory array will occur even though the
command was sent to just one Flash memory sec-
tor.
Flash Sector Erase. The Sector Erase instruc-
tion sequence uses six write operations, as de-
scribed in Table 5. Additional Flash Sector Erase
codes and Flash memory sector addresses can be
written subsequently to erase other Flash memory
sectors in parallel, without further coded cycles, if
the additional bytes are transmitted in a shorter
time than the time-out period of about 100 μs. The
input of a new Sector Erase code restarts the time-
out period.
The status of the internal timer can be monitored
through the level of the Erase Time-out Flag (DQ3)
bit. If the Erase Time-out Flag (DQ3) bit is 0, the
Sector Erase instruction sequence has been re-
ceived and the time-out period is counting. If the
Erase Time-out Flag (DQ3) bit is 1, the time-out
period has expired and the device is busy erasing
the Flash memory sector(s). Before and during
Erase time-out, any instruction sequence other
than Suspend Sector Erase and Resume Sector
Erase instruction sequences abort the cycle that is
currently in progress, and reset the device to Read
Array mode. It is not necessary to program the
Flash memory sector with 00h as the device does
this automatically before erasing (byte=FFh).
During a Sector Erase, the memory status may be
checked by reading the Error Flag (DQ5) bit, the
Toggle Flag (DQ6) bit, and the Data Polling Flag
(DQ7) bit, as detailed in the section entitled “Pro-
gramming Flash Memory”, on page 19.
DSM2190F4During execution of the Erase cycle, the Flash
memory accepts only Reset and Suspend Sector
Erase instruction sequences. Erasure of one
Flash memory sector may be suspended, in order
to read data from another Flash memory sector,
and then resumed.
The address provided with the initial Flash Sector
Erase command sequence (Table 5) must select
the first desired sector (FS0 - FS7 or CSBOOT0-
CSBOOT3) to erase. Subsequent sector erase
commands that are appended on within the time-
out period must be addressed to other desired
segments (FS0 - FS7 or CSBOOT0-CSBOOT3).
Suspend Sector Erase. When a Sector Erase
cycle is in progress, the Suspend Sector Erase in-
struction sequence can be used to suspend the
cycle by writing 0B0h to any address when an ap-
propriate Sector Select (FS0-FS7 or CSBOOT0-
CSBOOT3) is selected (See Table 5). This allows
reading of data from another Flash memory sector
after the Erase cycle has been suspended. Sus-
pend Sector Erase is accepted only during an
Erase cycle and defaults to Read mode. A Sus-
pend Sector Erase instruction sequence executed
during an Erase time-out period, in addition to sus-
pending the Erase cycle, terminates the time out
period.
The Toggle Flag (DQ6) bit stops toggling when the
device internal logic is suspended. The status of
this bit must be monitored at an address within the
Flash memory sector being erased. The Toggle
Flag (DQ6) bit stops toggling between 0.1 μs and
15 μs after the Suspend Sector Erase instruction
sequence has been executed. The device is then
automatically set to Read mode.
If an Suspend Sector Erase instruction sequence
was executed, the following rules apply: Attempting to read from a Flash memory sector
that was being erased outputs invalid data. Reading from a Flash memory sector that was
not being erased is valid. The Flash memory cannot be programmed, and
only responds to Resume Sector Erase and Re-
set Flash instruction sequences (Read is an op-
eration and is allowed). If a Reset Flash instruction sequence is re-
ceived, data in the Flash memory sector that
was being erased is invalid.
Resume Sector Erase. If a Suspend Sector
Erase instruction sequence was previously exe-
cuted, the erase cycle may be resumed with this
instruction sequence. The Resume Sector Erase
instruction sequence consists of writing 030h to
any address while an appropriate Sector Select
(FS0-FS7 or CSBOOT0-CSBOOT3) is active.
(See Table 5.)
Flash Memory Sector Protect.Each Flash memory sector can be separately pro-
tected against Program and Erase cycles. Sector
Protection provides additional data security be-
cause it disables all Program or Erase cycles. This
mode can be activated through the JTAG Port or a
Device Programmer. Sector protection can be se-
lected for each sector using PSDsoft Express.
This automatically protects selected sectors when
the device is programmed through the JTAG Port
or a Device Programmer. Flash memory sectors
can be unprotected to allow updating of their con-
tents using the JTAG Port or a Device Program-
mer. The DSP can read (but cannot change) the
sector protection bits.
Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a read of the protected data.
This allows a guarantee of the retention of the Pro-
tection status.
The sector protection status can be read by the
DSP through the Main Flash memory protection
register (in the csiop block) as defined in Table 7,
and Secondary Flash memory protection register
in Table 8.
Table 7. Main Flash Memory Protection Register DefinitionNote: Bit Definitions:
Sec_Prot 1 = Flash memory sector is write protected.
Sec_Prot 0 = Flash memory sector is not write protected.
Table 8. Secondary Flash Memory Protection/Security Bit Register DefinitionNote: Security_Bit = 1, device is secured.
Note:
Sec_Prot 1 = Flash memory sector is write protected.
Sec
_Prot 0 = Flash memory sector is not write protected.
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DSM2190F4
DSM Security Bit
A programmable security bit in the DSM protects
its contents from unauthorized viewing and copy-
ing. When set, the security bit will block access of
programming devices (JTAG or others) to the
DSM Flash memory and PLD configuration. The
only way to defeat the security bit is to erase the
entire DSM device, after which the device is blank
and may be used again. The DSP will always have
access to Flash memory contents through the 8-bit
data port even while the security bit is set. The
DSP can read the status of the security bit (but it
cannot change it) by reading the Device Security
register in the csiop block as defined in Table 8.
Reset Flash
The Reset Flash instruction sequence resets the
internal memory logic state machine and puts
Flash memory into Read Array mode. It consists of
one write cycle (see Table 5). It must be executed
after: Reading the Flash Protection Status or Flash ID An Error condition has occurred (and the device
has set the Error Flag (DQ5) bit to 1) during a
Flash memory Program or Erase cycle.
The Reset Flash instruction sequence puts the
Flash memory back into normal Read Array mode.
It may take the Flash memory up to a few millisec-
onds to complete the Reset cycle. The Reset
Flash instruction sequence is ignored when it is is-
sued during a Program or Bulk Erase cycle of the
Flash memory. The Reset Flash instruction se-
quence aborts any on-going Sector Erase cycle,
and returns the Flash memory to the normal Read
Array mode within a few milliseconds.
Page Register
The 8-bit Page Register increases the addressing
capability of the DSP by a factor of up to 256. The
contents of the register can also be read by the
DSP. The outputs of the Page Register (PG0-
PG7) are inputs to the DPLD decoder and can be
included in the Sector Select (FS0-FS7 or
CSBOOT0-CSBOOT3) equations. See Figure 12.
If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic. The eight flip-flops in the register are con-
nected to the internal data bus D0-D7. The DSP
can write to or read from the Page Register. The
Page Register can be accessed at address loca-
tion csiop + E0h. Page Register outputs are
cleared to logic 0 at reset.
Figure 12. Page Register
PLDs
The PLDs bring programmable logic to the device.
After specifying the logic for the PLDs using PSD-
soft Express, the logic is programmed into the de-
vice and available upon Power-up.
The PLDs have selectable levels of performance
and power consumption.
The device contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD), as shown
in Figure 13.
Table 9. DPLD and CPLD Inputs
Note:1. DSP address lines A16, A17, and others may enter the
DSM device on any pin on ports B, C, or D. See Figure 6
for recommended connections. Additional DSP control signals may enter the DMS device
on any pin on Ports B, C, or D. See Figure 6 for recom-
mended connections.
DSM2190F4
The DPLD performs address decoding, and gen-
erates select signals for internal and external com-
ponents, such as memory, registers, and I/O ports.
The DPLD can generates External Chip Select
(ECS0-ECS2) signals on Port D.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 16 Input Macrocells
(IMC), and the AND Array.
The AND Array is used to form product terms.
These product terms are configured from the logic
definition entered in PSDsoft Express. An Input
Bus consisting of 64 signals is connected to the
PLDs. Input signals are shown in Table 9.
Turbo Bit. The PLDs in the device can minimize
power consumption by switching off when inputs
remain unchanged for an extended time of about
70 ns. Resetting the Turbo bit to 0 (Bit 3 of the
PMMR0 register) automatically places the PLDs
into standby if no inputs are changing. Turning the
Turbo mode off increases propagation delays
while reducing power consumption. Additionally,
five bits are available in the PMMR registers in
csiop to block DSP control signals from entering
the PLDs. This reduces power consumption and
can be used only when these DSP control signals
are not used in PLD logic equations. Each of the
two PLDs has unique characteristics suited for its
applications. They are described in the following
sections.
Figure 13. PLD Diagram
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DSM2190F4
DECODE PLD (DPLD)
The DPLD, shown in Figure 14, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals: 8 Main Flash memory Sector Select (FS0-FS7)
signals with three product terms each 4 Secondary Flash memory Sector Select
(CSBOOT0-CSBOOT3) signals with three
product terms each 1 internal csiop select for DSM device control
and status registers (csiop is the base address
of the block of 256 byte locations) 1 JTAG Select signal (enables JTAG operations
on Port C when multiplexing JTAG signals with
general I/O signals) 3 external chip select output signals for Port D
pins, each with one product term.
DSM2190F4
COMPLEX PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. See application
note AN1171 for details on how to specify logic us-
ing PSDsoft Express.
As shown in Figure 15, the CPLD has the following
blocks: 16 Input Macrocells (IMC) 16 Output Macrocells (OMC) Macrocell Allocator Product Term Allocator AND Array capable of generating up to 130
product terms Two I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the device internal data
bus and can be directly accessed by the DSP. This
enables the DSP software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macro cell architectures.
Output Macrocell (OMC). Eight of the Output
Macrocells (OMC) are connected to Port B pins
and are named as McellAB0-McellAB7. The other
eight Macrocells are connected to Ports B or C
pins and are named as McellBC0-McellBC7.
OMCs may be used for internal feedback only
(buried registers), or their outputs may be routed
to external Port pins.
The Output Macrocell (OMC) architecture is
shown in Figure 17. As shown in the figure, there
are native product terms available from the AND
Array, and borrowed product terms available (if
unused) from other Output Macrocells (OMC). The
polarity of the product term is controlled by the
XOR gate. The Output Macrocell (OMC) can im-
plement either sequential logic, using the flip-flop
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DSM2190F4
element, or combinatorial logic. The multiplexer
selects between the sequential or combinatorial
logic outputs. The multiplexer output can drive a
port pin and has a feedback path to the AND Array
inputs.
The flip-flop in the Output Macrocell (OMC) block
can be configured as a D, T, JK, or SR type in PS-
Dsoft ExpressTM . The flip-flop’s clock, preset, and
clear inputs may be driven from a product term of
the AND Array. Alternatively, CLKIN (PD1) can be
used for the clock input to the flip-flop. The flip-flop
is clocked on the rising edge of CLKIN (PD1). The
preset and clear are active High inputs. Each clear
input can use up to two product terms.
Output Macrocell Allocator. Outputs of the 16
OMCs can be routed to a combination of pins on
Port B or Port D as shown in Figure 16. The OMC
output pin is automatically determined by
choosing pin functions in PSDsoft ExpressTM.
Routing can occur on a bit-by-bit basis, spitting
assignment between the Ports. However, one
OMC can be routed to one Port pin only, not both.
Figure 16. OMC Allocator
Table 10. Output Macrocell Port and Data Bit Assignments
Product Term Allocator. The CPLD has a Prod-
uct Term Allocator. PSDsoft ExpressTM uses the
Product Term Allocator to borrow and place prod-
uct terms from one Macrocell to another. This hap-
pens automatically in PSDsoft ExpressTM , but
understanding how allocation works will help you if
your logic design does not “fit”, in which case you
may try selecting a different pin or different OMC
where the allocation resources may differ and the
design will then fit. The following list summarizes
how product terms are allocated: McellAB0-McellAB7 all have three native
product terms and may borrow up to six more McellBC0-McellBC3 all have four native product
terms and may borrow up to five more McellBC4-McellBC7 all have four native product
terms and may borrow up to six more.
DSM2190F4
Each Macrocell may only borrow product terms
from certain other Macrocells. Product terms al-
ready in use by one Macrocell are not available for
another Macrocell. Product term allocation does
not add any propagation delay to the logic.
If an equation requires more product terms than
are available to it through product term allocation,
then “external” product terms are required, which
consumes other Output Macrocells (OMC). This is
called product term expansion and also happens
automatically in PSDsoft ExpressTM as needed.
Product tern expansion causes additional propa-
gation delay because an OMC is consumed by the
expansion and it’s output is rerouted (or fed back)
into the AND array.
You can examine the fitter report generated by
PSDsoft Express to see resulting product term al-
location and product term expansion.
Loading and Reading the Output Macrocells
(OMCs). Each of the two OMC blocks (8 OMCs
each) occupies a memory location in the DSP ad-
dress space, as defined in the csiop block
MCELLAB0-7 and MCELLBC0-7 (see Table 4).
The flip-flops in each of the 16 OMCs can be load-
ed from the data bus by a DSP. Loading the OMCs
with data from the DSP takes priority over internal
functions. As such, the preset, clear, and clock in-
puts to the flip-flop can be overridden by the DSP.
The ability to load the flip-flops and read them
back is useful in such applications as loadable
counters and shift registers, mailboxes, and hand-
shaking protocols.
Data is loaded into the Output Macrocells (OMC)
on the trailing edge of Write Strobe (WR, CNTL0).
Figure 17. CPLD Output Macrocell
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DSM2190F4
The OMC Mask Register. There is one Mask
Register for each of the two groups of eight Output
Macrocells (OMC). The Mask Registers can be
used to block the loading of data to individual Out-
put Macrocells (OMC). The default value for the
Mask Registers is 00h, which allows loading of the
Output Macrocells (OMC). When a given bit in a
Mask Register is set to a 1, the DSP is blocked
from writing to the associated Output Macrocells
(OMC). For example, suppose McellAB0-3 are be-
ing used for a state machine. You would not want
a DSP write to McellAB to overwrite the state ma-
chine registers. Therefore, you would want to load
the Mask Register for McellAB (Mask Macrocell
AB) with the value 0Fh.
The Output Enable of the OMC. The Output
Macrocells (OMC) block can be connected to an I/
O port pin as a PLD output. The output enable of
each port pin driver is controlled by a single prod-
uct term from the AND Array, ORed with the Direc-
tion Register output. The pin is enabled upon
Power-up if no output enable equation is defined
and if the pin is declared as a PLD output in PSD-
soft Express.
If the Output Macrocell (OMC) output is specified
as an internal node and not as a port pin output in
the PSDsoft Express, then the port pin can be
used for other I/O functions. The internal node
feedback can be routed as an input to the AND Ar-
ray.
Input Macrocells (IMC). The CPLD has 16 Input
Macrocells (IMC), one for each pin on Ports B and
C. The architecture of the IMCs is shown in Figure
18. The IMCs are individually configurable, and
can be used as a latch, a register, or to pass in-
coming Port signals prior to driving them onto the
PLD input bus. This is useful for sampling and de-
bouncing inputs to the AND array (keypad inputs,
etc.). Additionally, the outputs of the IMCs can be
read by the DSP asynchronously at any time
through the internal data bus using the csiop reg-
ister block (see Table 4).
The enable for the latch and clock for the register
are driven by a product term from the CPLD. Each
product term output is used to latch or clock four
IMCs. Port inputs 3-0 can be controlled by one
product term and 7-4 by another.
Configurations for the IMCs are specified by equa-
tions specified in PSDsoft Express. See Applica-
tion note AN1171.
DSM2190F4
DSP Bus Interface
The “no-glue logic” DSP Bus Interface allows di-
rect connection. DSP address, data, and control
signals connect directly to the DSM device. See
Figure 6 for typical connections.
DSP address, data and control signals are routed
to Flash memory, I/O control (csiop), OMCs, and
IMCs within the DMS. The DSP address range for
each of these components is specified in PSDsoft
ExpressTM.
I/O Ports
There are three programmable I/O ports: Ports B,
C, and D. Each of the ports is eight bits except Port
D, which is 3 bits. Each port pin is individually user
configurable, thus allowing multiple functions per
port. The ports are configured using PSDsoft Ex-
pressTM or by the DSP writing to on-chip registers
in the csiop block.
The topics discussed in this section are: General Port architecture Port operating modes Port Configuration Registers (PCR) Port Data Registers Individual Port functionality.
General Port Architecture. The general archi-
tecture of the I/O Port block is shown in Figure 19.
Individual Port architectures are shown in Figure
20 to Figure 23. In general, once the purpose for a
port pin has been defined in PSDsoft ExpressTM,
that pin is no longer available for other purposes.
Exceptions are noted.
As shown in Figure 19, the ports contain an output
multiplexer whose select signals are driven by the
configuration bits determined by PSDsoft Express.
Inputs to the multiplexer include the following: Output data from the Data Out register (for MCU
I/O mode) CPLD Macrocell output (OMC) External Chip Selects ESC0-2 from the DPLD to
Port D pins only.
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read by the
DSP. The Port Data Buffer (PDB) is connected to
the Internal Data Bus for feedback and can be
read by the DSP. The Data Out and Macrocell out-
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DSM2190F4
puts, Direction Registers, and port pin input are all
connected to the Port Data Buffer (PDB).
The Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is not defined as a CPLD output
in PSDsoft ExpressTM , then the Direction Register
has sole control of the buffer that drives the port
pin.
The contents of these registers can be altered by
the DSP. The Port Data Buffer (PDB) feedback
path allows the DSP to check the contents of the
registers.
Ports B, and C have embedded IMCs. The IMCs
can be configured as registers (for sampling or de-
bouncing), as transparent latches, or direct inputs
to the PLDs. The registers and latches are clocked
by a product term from the PLD AND Array. The
outputs from the IMCs drive the PLD input bus and
can be read by the DSP. See the section entitled
“Input Macrocell”, on page 29.
Port Operating Modes
The I/O Ports have several modes of operation.
Modes are defined using PSDsoft ExpressTM , and
then runtime control from the DSP can occur using
the registers in the csiop block. See Application
Note AN1171 for more detail.
Table 11 summarizes which modes are available
on each port. Each of the port operating modes
are described in the following sections.
Table 11. Port Operating Modes
Note:1. Can be multiplexed with other I/O functions.
MCU I/O Mode. In the MCU I/O mode, the DSP
uses the I/O Ports block to expand its own I/O
ports. The DSP can read I/O pins, set the direction
of I/O pins, and change the state of I/O pins by ac-
cessing the registers in the csiop block. The csiop
register definition and their addresses may be
found in Table 4.
The MCU I/O direction may be changed by writing
to the corresponding bit in the Direction Register,
or by the output enable product term. When the pin
is configured as an output, the content of the Data
Out Register drives the pin. When configured as
an input, the DSP can read the port input through
the Data In buffer. See Figure 19.
PLD I/O Mode. Inputs from Ports B and C to ei-
ther PLD (DPLD or CPLD) come through IMCs. In-
puts from Port D to either PLDs are routed directly
in and do not use IMCs. Outputs from the CPLD to
Port B come from the OMC group MCELLAB0-7.
Outputs from the CPLD to Port C come from OMC
group MCELLBC0-7. Outputs from the DPLD to
Port D come from the external chip select logic
block ECS0-2.
All PLD outputs may be tri-stated at the Port pins
with a control signal. This output enable control
signal can be defined by a product term from the
PLD, or by resetting the corresponding bit in the
Direction Register to 0. The corresponding bit in
the Direction Register must not be set to logic 1 by
the DSP if the pin is defined for a PLD input signal
in PSDsoft Express. The PLD I/O mode is defined
in PSDsoft Express by specifying PLD equations.
JTAG In-System Programming (ISP). Some of
the pins on Port C are based on the IEEE 1194.1
JTAG specification and is used for In-System Pro-
gramming (ISP). You can multiplex the function of
these Port C JTAG pins with other functions. ISP
is not performed very frequently in the life of the
product, so multiplexing these pin’s functions with
general purpose I/O functions gives more utility
from Port C. See the section entitled “Program-
ming In-Circuit Using JTAG ISP”, and Application
Note AN1153.
Port Configuration Registers (PCR). Each Port
has a set of Port Configuration Registers (PCR)
used for configuration of the pins. The contents of
the registers can be accessed by the DSP through
normal read/write bus cycles of the csiop registers
listed in Table 4.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a register refers to Bit 0 of its
