DS99R421QSQX/NOPB ,5-43 MHz FPD-Link LVDS (3 Data + 1 Clk) to FPD-Link II LVDS (Embedded Clk DC-Balanced) Conv 36-WQFN -40 to 105FEATURES DESCRIPTIONThe DS99R421 converts a FPD-Link input with 42• 5 MHz–43 MHz Embedded Clock & D ..
DSA010 , Stabkerndrosseln Iron core chokes Selfs baton de fer
DSA015 ,High-Speed Switching DiodeAbsolute Maximum Ratings at Ta= 25°C unitPeak Reverse Voltage VRM - 75 VReverse Voltage VR - 50 VSu ..
DSA12TE ,1.2A Power RectifierAbsolute Maximum Ratings at Ta = 25°C DSAIZTB DSA1fy 'C DSA12TE unitPeak Reverse Voltage VRM - 100 ..
DSA20C45PB , Schottky High Performance Schottky Diode Low Loss and Soft Recovery
DSA26C ,2.6A Power RectifierAbsolute Maximum Ratings at Ta= 25°C DSA26B DSAZSC DSAZGE unitPeak Reverse Voltage VRM - 100 - 200 ..
ED1402 ,NPN general purpose transistor
ED1402B ,NPN general purpose transistor
ED1402B ,NPN general purpose transistor
ED1402C ,NPN general purpose transistor
ED1402C ,NPN general purpose transistor
ED1402E ,NPN general purpose transistor
DS99R421QSQX/NOPB
5-43 MHz FPD-Link LVDS (3 Data + 1 Clk) to FPD-Link II LVDS (Embedded Clk DC-Balanced) Conv
DS99R421
www.ti.com SNLS264D–JUNE 2007–REVISED APRIL 2013
5-43 MHz FPD-Link LVDS(3 Data+1 Clock) to FPD-LinkII LVDS (Embedded Clock DC-
Balanced) Converter
Checkfor Samples: DS99R421
1FEATURES DESCRIPTIONThe DS99R421 convertsa FPD-Link input with4
5 MHz–43 MHz Embedded Clock& DC- non-DC Balanced LVDS (3 LVDS Data+ LVDS
Balanced Data Transmission (21 Total LVDS Clock) plus3 over-sampled low speed control bits
Data Bits Plus3 Low Speed LVCMOS Data intoa single LVDS DC-balanced serial stream with
Bits) embedded clock information. This single serial stream
User Adjustable Pre-Emphasis Driving Ability simplifies transferring the 24-bit bus overa single
Through External Resistor on LVDS Outputs differential pair of PCB traces and cable by
eliminating the skew problems between the3 parallel
and Capableto Drive upto10 Meters ShieldedLVDS data inputs and LVDS clock paths.It saves
Twisted-Pair Cable system cost by narrowing4 LVDS pairsto1 LVDS
• Supports AC-Coupling Data Transmission pair thatin turn reduce PCB layers, cable width,
• 100Ω Integrated Termination Resistorat LVDS connector size, and pins.
Input The DS99R421 incorporatesa single serialized LVDS
• Power-Down Control signalon the high-speed I/O. Embedded clock LVDS
Available @SPEED BISTto DS90UR124to providesa low power and low noise environment for
Validate Link Integrity reliably transferring data overa serial transmission
path. By optimizing the converter output edge rate for
• All LVCMOS Inputs& Control Pins Have the operating frequency range EMIis further reduced.
Internal Pulldown addition the device features pre-emphasisto boost
• Schmitt Trigger Inputs on OS[2:0]to Minimize signals over longer distances using lossy cables.
Metastable Conditions Internal DC balanced encodingis usedto support
• Outputs Tri-Stated Through DEN AC-Coupled interconnects.
On-Chip Filters for PLLs Power Supply Range 3.3V± 10% Automotive Temperature Range −40°Cto
+105°C Greater Than 8kV ESD Tolerance Meets ISO 10605 ESD and AEC-Q100
