DS92LV1224TMSA/NOPB ,30-66 MHz 10-Bit Deserializer 28-SSOP -40 to 85Functional DescriptionThe DS92LV1224 is a 10-bit Deserializer device which together with a compatib ..
DS92LV1224TMSA/NOPB ,30-66 MHz 10-Bit Deserializer 28-SSOP -40 to 85 SNLS189A –APRIL 2005–REVISED APRIL 2013After determining which clock edge to use, a start and stop ..
DS92LV1224TMSAX ,40 MHz-66MHz 10-Bit DeserializerGeneral Description®put pins into TRI-STATE to achieve a high impedanceThe DS92LV1023 transforms a ..
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DS92LV1224TMSA/NOPB
30-66 MHz 10-Bit Deserializer 28-SSOP -40 to 85
L-T
-SE
RIA
CONTROL
10-BIT SERIALIZERDIN DO+
DO-
DEN
RIA
T LA
RI+
RI-
LVDS
DS92LV1224CLOCK
RECOVERY
ROUT
REFCLK
REN
LOCK
DS92LV1224
www.ti.com SNLS189A–APRIL 2005–REVISED APRIL 2013
DS92LV1224 30-66 MHz 10 Bit Bus LVDS Deserializer
Checkfor Samples: DS92LV1224
1FEATURES DESCRIPTIONThe DS92LV1224isa 300to 660 Mb/s deserializer
30–66 MHz Single 1:10 Deserializer with for high-speed unidirectional serial data transmission
300–660 Mb/s Throughput over FR-4 printed circuit board backplanes and
• Robust Bus LVDS Serial Data Transmission balanced copper cables.It receives the Bus LVDS
with Embedded Clock for Exceptional Noise serial data stream froma compatible 10–bit serializer,
Immunity and Low EMI transformsit back intoa 10-bit wide parallel data bus
and recovers parallel clock. This single serial data
• Clock Recovery from PLL Lockto Random stream simplifies PCB design and reduces PCB cost
Data Patterns by narrowing data paths thatin turn reduce PCB size
• Ensured Transition Every Data Transfer Cycle and numberof layers. The single serial data stream
Low Power Consumption< 300 mW (typ) also reduces cable size, the numberof connectors,
66 MHz and eliminates clock-to-data and data-to-data skew.
Single Differential Pair Eliminates Multi- The DS92LV1224 works well with Bus LVDS 10–bit
Channel Skew serializers within its specified frequency operating
range.It features low power consumption, and high
• Flow-Through Pinout for Easy PCB Layout impedance outputsin power down mode.
• Synchronization Mode and LOCK IndicatorThe DS92LV1224 was designed with the flow-through
• Programmable Edge Trigger on Clock pinout andis availableina space saving 28–lead
• High Impedance on Receiver Inputs when SSOP package.
Poweris Off Small 28-Lead SSOP Package
Block Diagrams
