DS92LV1212AMSA ,16 MHzfeatures of the DS92LV1212. The n Guaranteed transition every data transfer cycleDS92LV1212A is des ..
DS92LV1212AMSA/NOPB ,16 MHzBlock DiagramDS101387-1®TRI-STATE is a registered trademark of National Semiconductor Corporation. ..
DS92LV1212AMSAX ,16 MHzFeaturesn Clock recovery without SYNC patterns-random lockThe DS92LV1212A is an upgrade of the DS92 ..
DS92LV1212AMSAX/NOPB ,16 MHzfeatures of the DS92LV1212. The n Guaranteed transition every data transfer cycleDS92LV1212A is des ..
DS92LV1212TMSA ,16 MHzFunctional Descriptionclock, the LOCK output will go low. When LOCK is low theThe DS92LV1212 is a 1 ..
DS92LV1224TMSA ,40 MHz-66MHz 10-Bit DeserializerDS92LV1023 and DS92LV1224 40-66 MHz 10 Bit Bus LVDS Serializer and DeserializerJune 2002DS92LV1023 ..
DS92LV1212AMSA-DS92LV1212AMSAX
16 MHz
DS92LV1212A
16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer
with Embedded Clock Recovery
General DescriptionThe DS92LV1212Aisan upgradeof the DS92LV1212.It
maintainsallof the featuresof the DS92LV1212. The
DS92LV1212Ais designedtobe used withthe DS92LV1021
Bus LVDS Serializer. The DS92LV1212A receivesa Bus
LVDS serial data stream and transformsit intoa 10-bit wide
parallel data bus and separate clock. The reduced cable,
PCB trace count and connector size saves cost and makes
PCB layout easier. Clock-to-data and data-to-data skewsare
eliminated since one input receives both clock and data bits
serially. The powerdownpinis usedto save powerby reduc-
ing the supply current when the deviceis notin use. The
Deserializer will establish locktoa synchronization pattern
within specified lock times butit can also locktoa data
stream without SYNC patterns.
Features Clock recovery without SYNC patterns-random lock Guaranteed transition every data transfer cycle Chipset (Tx+ Rx) power consumption< 300mW (typ)@
40MHz Single differential pair eliminates multi-channel skew 400 Mbps serial Bus LVDS bandwidth(at40 MHz clock) 10-bit parallel interfacefor1 byte data plus2 control bits UTOPIAI Interface Synchronization mode and LOCK indicator Flow-through pinoutfor easy PCB layout High impedanceon receiver inputs when powerisoff Programmable edge triggeron clock Footprint compatible with DS92LV1210 Small 28-lead SSOP package-MSA
Block DiagramDS101387-1
November 2000
DS92L
V1212A
MHz
10-Bit
Bus
VDS
Random
Lock
Deserializer
with
Embedded
Clock
Recovery
