DS92LV1023TMSAX ,40 MHz-66MHz 10-Bit SerializerBlock Diagrams10093301®TRI-STATE is a registered trademark of National Semiconductor Corporation. 2 ..
DS92LV1210TMSA ,16 MHzGeneral Description®pins may be TRI-STATE to achieve a high impedanceThe DS92LV1021 transforms a 10 ..
DS92LV1210TMSA ,16 MHzBlock Diagrams (Continued)Application10011002Control of the sync pins is left to the user. A feedba ..
DS92LV1210TMSA ,16 MHzFeatures10-bit wide parallel data bus and separates clock. Then Guaranteed transition every data tr ..
DS92LV1212AMSA ,16 MHzfeatures of the DS92LV1212. The n Guaranteed transition every data transfer cycleDS92LV1212A is des ..
DS92LV1212AMSA/NOPB ,16 MHzBlock DiagramDS101387-1®TRI-STATE is a registered trademark of National Semiconductor Corporation. ..
DS92LV1023TMSA-DS92LV1023TMSAX-DS92LV1224TMSA-DS92LV1224TMSAX
40 MHz-66MHz 10-Bit Serializer
DS92LV1023 and DS92LV1224
40-66 MHz 10 Bit Bus LVDS Serializer and Deserializer
General DescriptionThe DS92LV1023 transformsa 10-bit wide parallel
LVCMOS/LVTTL data bus intoa single high speed Bus
LVDS serial data stream with embedded clock. The
DS92LV1224 receivesthe Bus LVDS serial data stream and
transformsit back intoa 10-bit wide parallel data bus and
recovers parallel clock. The DS92LV1023 transmits data
over backplanesor cable. The single differential pair data
path makes PCB design easier.In addition, the reduced
cable, PCB trace count, and connector size tremendously
reduce cost. Since one output transmits clock and data bits
serially,it eliminates clock-to-data and data-to-data skew.
The powerdownpin saves powerby reducing supply current
whennot using either device. Upon powerupof the Serial-
izer, you can chooseto activate synchronization modeor
allow the Deserializer to use the
synchronization-to-random-data feature.By using the syn-
chronization mode, the Deserializer will establish locktoa
signal within specified lock times.In addition,the embedded
clock guaranteesa transitionon the bus every 12-bit cycle.
This eliminates transmission errors dueto charged cable
conditions. Furthermore, you mayputthe DS92LV1023 out-
put pins into TRI-STATE®to achievea high impedance
state. The PLL can lockto frequencies between40 MHz and MHz.
Features Clock recovery from PLL lockto random data patterns. Guaranteed transition every data transfer cycle Chipset (Tx+ Rx) power consumption< 500 mW (typ)66 MHz Single differential pair eliminates multi-channel skew Flow-through pinoutfor easy PCB layout 660 Mbps serial Bus LVDS data rate(at66 MHz clock) 10-bit parallel interfacefor1 byte data plus2 control bits Synchronization mode and LOCK indicator Programmable edge triggeron clock High impedanceon receiver inputs when powerisoff Bus LVDS serial output ratedfor 27Ω load Small 28-lead SSOP package
Block DiagramsJune 2002
DS92L
V1023
and
DS92L
V1224
MHz
Bit
Bus
VDS
Serializer
and
Deserializer
