DS92LV1021TMSAX ,16 MHzDS92LV1021 and DS92LV1210 16-40 MHz 10 Bit Bus LVDS Serializer and DeserializerDecember 2002DS92LV1 ..
DS92LV1023EMQ , 30-66 MHz 10 Bit Bus LVDS Serializer
DS92LV1023EMQ/NOPB ,30-66 MHz 10-Bit Serializer 28-SSOP -40 to 85 SNLS187B –MARCH 2005–REVISED APRIL 2013Data TransferAfter initialization, the Serializer will acce ..
DS92LV1023TMSA ,40 MHz-66MHz 10-Bit SerializerFeaturestransforms it back into a 10-bit wide parallel data bus andn Clock recovery from PLL lock t ..
DS92LV1023TMSA/NOPB ,40-66 MHz 10-Bit Serializer 28-SSOP SNLS049D –MAY 2000–REVISED APRIL 2013Data TransferAfter initialization, the Serializer will accept ..
DS92LV1023TMSAX ,40 MHz-66MHz 10-Bit SerializerBlock Diagrams10093301®TRI-STATE is a registered trademark of National Semiconductor Corporation. 2 ..
DS92LV1021TMSA-DS92LV1021TMSAX-DS92LV1210TMSA
16 MHz
DS92LV1021 and DS92LV1210
16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer
General DescriptionThe DS92LV1021 transformsa 10-bit wide parallel CMOS/
TTL data bus intoa single high speed Bus LVDS serial data
stream with embedded clock. The DS92LV1210 receivesthe
Bus LVDS serial data stream and transformsit back intoa
10-bit wide parallel data bus and separates clock. The
DS92LV1021 may transmit data over heavily loaded back-
planesor10 metersof cable. The reduced cable, PCB trace
count and connector size saves cost and makes PCB design
layout easier. Clock-to-data and data-to-data skeware elimi-
nated since one outputwill transmit both clock andall data
bits serially. The powerdown pinis usedto save power,by
reducing supply current when either deviceisnotin use. The
Serializer hasa synchronization mode that shouldbe acti-
vated upon power-upof the device. The Deserializer will
establish lockto this signal within 1024 cycles, andwill flag
Lock status. The embedded clock guaranteesa transitionon
the bus every 12-bit cycle; eliminating transmission errors
dueto charged cable conditions. The DS92LV1021 output
pins maybe TRI-STATE®to achievea high impedance
state. The PLL can lockto frequencies between16 MHz and MHz.
Features Guaranteed transition every data transfer cycle Single differential pair eliminates multi-channel skew Flow-through pinoutfor easy PCB layout 400 Mbps serial Bus LVDS bandwidth(at40 MHz clock) 10-bit parallel interfacefor1 byte data plus2 control bits Synchronization mode and LOCK indicator Programmable edge triggeron clock High impedanceon receiver inputs when powerisoff Bus LVDS serial output ratedfor 27Ω load Small 28-lead SSOP package-MSA
Block DiagramsDecember 2002
DS92L
V1021
and
DS92L
V1210
MHz
Bit
Bus
VDS
Serializer
and
Deserializer
