DS92LV1021AMSAX ,16 MHzFeatureseasier. In addition, the reduced cable, PCB trace count, andn Guaranteed transition every d ..
DS92LV1021TMSA ,16 MHzGeneral Description®pins may be TRI-STATE to achieve a high impedanceThe DS92LV1021 transforms a 10 ..
DS92LV1021TMSAX ,16 MHzDS92LV1021 and DS92LV1210 16-40 MHz 10 Bit Bus LVDS Serializer and DeserializerDecember 2002DS92LV1 ..
DS92LV1023EMQ , 30-66 MHz 10 Bit Bus LVDS Serializer
DS92LV1023EMQ/NOPB ,30-66 MHz 10-Bit Serializer 28-SSOP -40 to 85 SNLS187B –MARCH 2005–REVISED APRIL 2013Data TransferAfter initialization, the Serializer will acce ..
DS92LV1023TMSA ,40 MHz-66MHz 10-Bit SerializerFeaturestransforms it back into a 10-bit wide parallel data bus andn Clock recovery from PLL lock t ..
DS92LV1021A-DS92LV1021AMSA-DS92LV1021AMSAX
16 MHz
DS92LV1021A
16-40 MHz 10 Bit Bus LVDS Serializer
General DescriptionThe DS92LV1021A transformsa 10-bit wide parallel
LVCMOS/LVTTL data bus intoa single high speed Bus
LVDS serial data stream with embedded clock. The
DS92LV1021A can transmit data over backplanesor cable.
The single differential pair data path makes PCB design
easier.In addition,the reduced cable, PCB trace count, and
connector size tremendously reduce cost. Since one output
transmits both clock and data bits serially,it eliminates clock-
to-data and data-to-data skew. The powerdown pin saves
powerby reducing supply current when the deviceis not
being used. Upon powerupofthe Serializer, you can choose activate synchronization modeor use oneof National
Semiconductor’s Deserializersin the synchronization-to-
random-data feature.By using the synchronization mode,
the Deserializerwill establish locktoa signal within specified
lock times.In addition, the embedded clock guaranteesa
transitionon the bus every 12-bit cycle. This eliminates
transmission errors dueto charged cable conditions. Fur-
thermore, you may put the DS92LV1021A output pins into
TRI-STATE®to achievea high impedance state. The PLL
can lockto frequencies between16 MHz and40 MHz.
Features Guaranteed transition every data transfer cycle Single differential pair eliminates multi-channel skew Flow-through pinoutfor easy PCB layout 400 Mbps serial Bus LVDS bandwidth(at40 MHz clock) 10-bit parallel interfacefor1 byte data plus2 control bits Programmable edge triggeron clock Bus LVDS serial output ratedfor 27Ω load Small 28-lead SSOP package-MSA
Block DiagramsJanuary 2003
DS92L
V1021A
MHz
Bit
Bus
VDS
Serializer
