DS92LV090ATVEH/NOPB ,9 Channel Bus LVDS Transceiver 64-LQFP -40 to 85features a flow through pinID200mV out which allows easy PCB routing for short stubsbetween its pin ..
DS92LV090ATVEHX ,9 Channel Bus LVDS TransceiverApplicationstypicalInformation Section for more details.)n Receiver Channel to Channel skew (same d ..
DS92LV090ATVEHX ,9 Channel Bus LVDS Transceiverfeatures a flow through pin outn Supports open and terminated failsafe on port pinswhich allows eas ..
DS92LV1021A ,16 MHzGeneral Descriptiontransmission errors due to charged cable conditions. Fur-The DS92LV1021A transfo ..
DS92LV1021AMSA ,16 MHzDS92LV1021A 16-40 MHz 10 Bit Bus LVDS SerializerJanuary 2003DS92LV1021A16-40 MHz 10 Bit Bus LVDS Se ..
DS92LV1021AMSAX ,16 MHzFeatureseasier. In addition, the reduced cable, PCB trace count, andn Guaranteed transition every d ..
DS92LV090ATVEH/NOPB
9 Channel Bus LVDS Transceiver 64-LQFP -40 to 85
DS92LV090A
www.ti.com SNLS025D–APRIL 2000–REVISED APRIL 2013
DS92LV090A9 Channel Bus LVDS Transceiver
Checkfor Samples: DS92LV090A
1FEATURES DESCRIPTIONThe DS92LV090Ais oneina seriesof Bus LVDS
Bus LVDS Signaling transceivers designed specifically for the high speed,
• 3.2 Nanosecond Propagation Delay Max low power proprietary backplaneor cable interfaces.
Chipto Chip Skew ±800ps The device operates froma single 3.3V power supply
and includes nine differential line drivers and nine
• Low Power CMOS Design receivers. To minimize bus loading, the driver outputs
• High Signaling Rate Capability (Above 100 and receiver inputs are internally connected. The
Mbps) separate I/Oof the logic side allows for loop back
0.1Vto 2.3V Common Mode Range for VID= support. The device also featuresa flow through pin
200mV out which allows easy PCB routing for short stubs
betweenits pins and the connector.
• ±100 mV Receiver SensitivityThe driver translates 3V TTL levels (single-ended)to
• Supports Open and Terminated Failsafe ondifferential Bus LVDS (BLVDS) output levels. This
Port Pins allows for high speed operation, while consuming
• 3.3V Operation minimal power with reduced EMI. In addition, the
• Glitch Free Power Up/Down (Driver& Receiver differential signaling provides common mode noise
Disabled) rejectionof ±1V.
Light Bus Loading(5 pF Typical) per Bus The receiver thresholdis less than ±100 mV overa
LVDS Load ±1V common mode range and translates the
differential Bus LVDS to standard (TTL/CMOS)
• Designed for Double Termination Applicationslevels. (See Applications Information Sectionfor more
• Balanced Output Impedance details.)
• Product Offeredin64 Pin LQFP Package High Impedance Bus Pins on Power off (VCC=
0V) Driver Channelto Channel Skew (Same
Device) 230ps Typical Receiver Channelto Channel Skew (Same
Device) 370ps Typical Diagram
Figure1.
