DS92LV090A ,9 Channel Bus LVDS TransceiverFeaturesn Bus LVDS SignalingThe DS92LV090A is one in a series of Bus LVDS transceiv-ers designed sp ..
DS92LV090ATVEH ,9 Channel Bus LVDS TransceiverFeaturesn Bus LVDS SignalingThe DS92LV090A is one in a series of Bus LVDS transceiv-ers designed sp ..
DS92LV090ATVEH/NOPB ,9 Channel Bus LVDS Transceiver 64-LQFP -40 to 85features a flow through pinID200mV out which allows easy PCB routing for short stubsbetween its pin ..
DS92LV090ATVEHX ,9 Channel Bus LVDS TransceiverApplicationstypicalInformation Section for more details.)n Receiver Channel to Channel skew (same d ..
DS92LV090ATVEHX ,9 Channel Bus LVDS Transceiverfeatures a flow through pin outn Supports open and terminated failsafe on port pinswhich allows eas ..
DS92LV1021A ,16 MHzGeneral Descriptiontransmission errors due to charged cable conditions. Fur-The DS92LV1021A transfo ..
DS92LV090A
9 Channel Bus LVDS Transceiver
DS92LV090A Channel Bus LVDS Transceiver
General DescriptionThe DS92LV090Ais oneina seriesof Bus LVDS transceiv-
ers designed specificallyfor the high speed, low power
proprietary backplaneor cable interfaces. The device oper-
ates froma single 3.3V power supply and includes nine
differential line drivers and nine receivers.To minimize bus
loading, the driver outputs and receiver inputsare internally
connected. The separateI/Oofthe logic side allowsfor loop
back support. The device also featuresa flow throughpinout
which allows easy PCB routingfor short stubs betweenits
pins andthe connector.
The driver translates3V TTL levels (single-ended)to differ-
ential Bus LVDS (BLVDS) output levels. This allowsfor high
speed operation, while consuming minimal power withre-
duced EMI.In addition, the differential signaling provides
common mode noise rejectionof ±1V.
The receiver thresholdis less than ±100 mV overa ±1V
common mode range and translates the differential Bus
LVDSto standard (TTL/CMOS) levels. (See Applications
Information Sectionfor more details.)
Features Bus LVDS Signaling 3.2 nanosecond propagation delay max Chipto Chip skew ±800ps Low power CMOS design High Signaling Rate Capability (above 100 Mbps) 0.1Vto 2.3V Common Mode Rangefor VID= 200mV ±100 mV Receiver Sensitivity Supports open and terminated failsafeon port pins 3.3V operation Glitch free power up/down (Driver& Receiver disabled) Light Bus Loading(5pF typical) per Bus LVDS load Designedfor Double Termination Applications Balanced Output Impedance Product offeredin64pin TQFP package High impedance Bus pinson poweroff (VCC= 0V) Driver Channelto Channel skew (same device) 230ps
typical Receiver Channelto Channel skew (same device)
370ps typical
Simplified Functional DiagramDS100111-1
February 2001
DS92L
V090A
Channel
Bus
VDS
ransceiver
