DS92LV010ATM ,Bus LVDS 3.3/5.0V Single TransceiverfeaturesflowthroughwhichallowseasyPCBroutingforn Glitch free power up/down (Driver disabled)short s ..
DS92LV010ATMX ,Bus LVDS 3.3/5.0V Single TransceiverGeneral Descriptionmode range and translates the low voltage differential levelsTheDS92LV010Aisonei ..
DS92LV010ATMX/NOPB ,Bus LVDS 3.3/5.0V Single Transceiver 8-SOIC -40 to 85ELECTRICAL CHARACTERISTICST =−40°C to +85°C unless otherwise noted, V = 3.3V ± 0.3VA CCParameter Te ..
DS92LV010ATMXNOPB ,Bus LVDS 3.3/5.0V Single Transceiver 8-SOIC -40 to 85features flow through which• ±100mV Receiver Sensitivityallows easy PCB routing for short stubs bet ..
DS92LV040ATLQA ,4 Channel Bus LVDS TransceiverElectrical CharacteristicsOver recommended operating supply voltage and temperature ranges unless o ..
DS92LV040ATLQA ,4 Channel Bus LVDS TransceiverApplications Information Section formore details.) n Product offered in 44 pin LLP (Leadless Leadfr ..
DS92LV010ATM-DS92LV010ATMX
Bus LVDS 3.3/5.0V Single Transceiver
DS92LV010A
Bus LVDS 3.3/5.0V Single Transceiver
General DescriptionThe DS92LV010Ais oneina seriesof transceivers designed
specificallyfor the high speed, low power proprietary bus
backplane interfaces. The device operates froma single
3.3Vor 5.0V power supply and includes one differential line
driver and one receiver.To minimize bus loading the driver
outputs and receiver inputs are internally connected. The
logic interface provides maximum flexibilityas4 separate
lines are provided (DIN, DE, RE, and ROUT). The device
also features flow through which allows easy PCB routingfor
short stubs between the bus pins and the connector. The
driver has10 mA drive capability, allowingitto drive heavily
loaded backplanes, with impedanceas lowas27 Ohms.
The driver translates between TTL levels (single-ended)to
Low Voltage Differential Signaling levels. This allowsfor high
speed operation, while consuming minimal power withre-
duced EMI.In addition the differential signaling provides
common mode noise rejectionof ±1V.
The receiver thresholdis ±100mV overa ±1V common
mode range and translatesthe low voltage differential levels standard (CMOS/TTL) levels.
Features Bus LVDS Signaling (BLVDS) Designedfor Double Termination Applications Balanced Output Impedance Lite Bus Loading 5pF typical Glitch free power up/down (Driver disabled) 3.3Vor 5.0V Operation ±1V Common Mode Range ±100mV Receiver Sensitivity High Signaling Rate Capability (above 100 Mbps) Low Power CMOS design Product offeredin8 lead SOIC package Industrial Temperature Range Operation
Connection DiagramOrder Number DS92LV010ATM
SeeNS Package Number M08A
Block Diagram
February 2005
DS92L
V010A
Bus
VDS
3.3/5.0V
Single
ransceiver
