DS92CK16TMTC ,3V BLVDS 1 to 6 Clock Buffer/Bus Transceiverapplications requir-n 50 ps channel to channel skew (typical)ing ultra low power dissipation, low n ..
DS92CK16TMTCX ,3V BLVDS 1 to 6 Clock Buffer/Bus TransceiverPin DescriptionPin Name Pin # Type DescriptionCLKI/O+ 6 I/O True (Positive) side of the differentia ..
DS92LV010ATM ,Bus LVDS 3.3/5.0V Single TransceiverfeaturesflowthroughwhichallowseasyPCBroutingforn Glitch free power up/down (Driver disabled)short s ..
DS92LV010ATMX ,Bus LVDS 3.3/5.0V Single TransceiverGeneral Descriptionmode range and translates the low voltage differential levelsTheDS92LV010Aisonei ..
DS92LV010ATMX/NOPB ,Bus LVDS 3.3/5.0V Single Transceiver 8-SOIC -40 to 85ELECTRICAL CHARACTERISTICST =−40°C to +85°C unless otherwise noted, V = 3.3V ± 0.3VA CCParameter Te ..
DS92LV010ATMXNOPB ,Bus LVDS 3.3/5.0V Single Transceiver 8-SOIC -40 to 85features flow through which• ±100mV Receiver Sensitivityallows easy PCB routing for short stubs bet ..
DS92CK16TMTC-DS92CK16TMTCX
3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver
DS92CK16 BLVDS1 to6 Clock Buffer/Bus Transceiver
General DescriptionThe DS92CK161to6 Clock Buffer/Bus Transceiveris aonesix CMOS differentialclock distributiondevice utilizingBus
Low Voltage Differential Signaling (BLVDS) technology. This
clock distribution deviceis designedfor applications requir-
ing ultralow power dissipation,low noise, and high data
rates.The BLVDSsideisa transceiverwitha separate chan-
nel actingasa return/source clock.
The DS92CK16 accepts BLVDS (300mV typical) differential
input levels,and translates themto3V CMOS output levels. output enablepinOE ,when high, forces allCLKOUTpins
high.
The devicecanbe useda source synchronous driver. The
selectionofthe source drivingis controlledbythe CrdCLKIN
andDE pins.Thisdevicecan bethe master clock, drivingthe
inputsof other clockI/O pinsina multipoint environment.
Easy master/slave clock selectionis achieved alonga back-
plane.
Features Master/Slave clock selectionina backplane application 125 MHz operation (typical) 100ps duty cycle distortion (typical)50ps channelto channel skew (typical) 3.3V power supply design Glitch-free poweronat CLKI/O pins Low Power design(20mA@ 3.3V static) Accepts small swing (300mV typical) differential signal
levels Industrial temperature operating range (-40˚Cto +85˚C) Availablein 24-pin TSSOP Packaging
Function Diagram and Truth Table
Receive Mode Truth Table
INPUT OUTPUT DE CrdCLKIN (CLKI/O+)–(CLKI/O−) CLKOUT X X H H X VID≥ 0.07V H H X VID≤ −0.07V L=Low LogicState=High Logic State= Irrelevant= TRI-STATE
Driver Mode Truth Table
INPUT OUTPUT DE CrdCLKIN CLK/I/O+ CLKI/O− CLKOUT L L H L H H L H L L H H H H L H X Z Z H
TRI-STATE®isa registeredtrademark ofNationalSemiconductorCorporation.
DS101082-1
November 1999
DS92CK16
VDS
Clock
Buffer/Bus
ransceiver©1999 National Semiconductor Corporation DS101082
