DS92001TLD ,3.3V B/LVDS-BLVDS BufferElectrical Characteristics (Continued)Over recommended operating supply and temperature ranges unle ..
DS92001TMA ,3.3V B/LVDS-BLVDS BufferBlock DiagramsSOIC - Top View2002470220024705Functional OperationLLP - Top ViewBLVDS Inputs BLVDS O ..
DS92CK16TMTC ,3V BLVDS 1 to 6 Clock Buffer/Bus Transceiverapplications requir-n 50 ps channel to channel skew (typical)ing ultra low power dissipation, low n ..
DS92CK16TMTCX ,3V BLVDS 1 to 6 Clock Buffer/Bus TransceiverPin DescriptionPin Name Pin # Type DescriptionCLKI/O+ 6 I/O True (Positive) side of the differentia ..
DS92LV010ATM ,Bus LVDS 3.3/5.0V Single TransceiverfeaturesflowthroughwhichallowseasyPCBroutingforn Glitch free power up/down (Driver disabled)short s ..
DS92LV010ATMX ,Bus LVDS 3.3/5.0V Single TransceiverGeneral Descriptionmode range and translates the low voltage differential levelsTheDS92LV010Aisonei ..
DS92001TLD-DS92001TMA
3.3V B/LVDS-BLVDS Buffer
DS92001
3.3V B/LVDS-BLVDS Buffer
General DescriptionThe DS92001 B/LVDS-BLVDS Buffer takesa BLVDS input
signal and providesan BLVDS output signal.In many large
systems, signals are distributed across backplanes, and onethe limiting factorsfor system speedisthe ’stub length’or
the distance between the transmission line andthe untermi-
nated receiverson individual cards. Althoughitis generally
recognized that this distance shouldbeas shortas possible maximize system performance, real-world packaging con-
cerns often makeit difficultto makethe stubsas shortasthe
designer would like.
The DS92001 has edge transitions optimizedfor multidrop
backplanes wherethe switching frequencyisinthe 200 MHz
rangeor less. The output edge rateis criticalin some sys-
tems where long stubs maybe present, and utilizinga slow
transition allowsfor longer stub lengths.
The DS92001, availablein the LLP (Leadless Leadframe
Package) package,will allowthe receiver inputstobe placed
very closeto the main transmission line, thus improving
system performance. wide input dynamic range allowsthe DS92001to receive
differential signals from LVPECLas wellas LVDS sources.
Thiswill allow the deviceto alsofill the roleofan LVPECL-
BLVDS translator.
The LOSpin detectsa non-driven B/LVDS bus stateat the
input and providesan active LOW output. The LOSpin can tiedto the device’s output enablepin (EN)to generatea
TRI-STATE output state when the inputis un-driven. The
LOSpin can alsobe used locallyto informthe systemofthe
bus state.
Features Single +3.3V Supply B/LVDS receiver inputs accept LVPECL signals TRI-STATE outputs Lossof Signal (LOS)pin detectsa non-driven bus Receiver input threshold< ±100 mV Fast propagation delayof 1.4ns (typ) Low jitter 400 Mbps fully differential data path Compatible with BLVDS 10-bit SerDes (40MHz) Compatible with ANSI/TIA/EIA-644-A LVDS standard Availablein SOIC and space saving LLP package Industrial Temperature Range
Connection and Block Diagrams
SOIC- Top ViewLLP- Top View
DAP (GND)PadNot Shown
Functional Operation
BLVDS Inputs BLVDS Outputs
[IN+]− [IN−] OUT+ OUT−
VID≥ 0.1V H L
VID≤ −0.1V L H
Full Fail-safe
OPEN/SHORTor Terminated
Ordering InformationOrder Number NS Pkg. No. Pkg. Type
DS92001TM M08A SOIC
DS92001TLD LDA08A LLP
June 2002
DS92001
3.3V
B/L
VDS-BL
VDS
Buffer
