DS90UR124IVSX/NOPB ,5-43MHz DC-Balanced 24-Bit FPD-Link II Deserializer 64-TQFP -40 to 105features pre-emphasis to boost signals over longer distances using lossy cables. InternalDC-balance ..
DS90UR124QVSX , 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset
DS90UR241QVS , 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset
DS90UR241QVS , 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset
DS90UR241QVSX/NOPB ,5-43MHz DC-Balanced 24-Bit FPD-Link II Serializer 48-TQFP -40 to 105Features 2 Applications1• Supports Displays With 18-Bit Color Depth • Automotive Central Informatio ..
DS90UR903QSQ/NOPB ,10Features 3 DescriptionThe DS90UR903Q/DS90UR904Q chipset offers a1• 10 MHz to 43 MHz Input PCLK Supp ..
DS90UR124IVS/NOPB-DS90UR124IVSX/NOPB
5-43MHz DC-Balanced 24-Bit FPD-Link II Deserializer
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Features 2 Applications Supports Displays With 18-Bit Color Depth • Automotive Central Information 5-MHzto 43-MHz Pixel Clock • Automotive Instrument Automotive-Grade Product AEC-Q100 Grade2 • Automotive Heads-Up
Qualified • Remote Camera-Based Driver Assistance 24:1 Interface Compression Systems Embedded Clock With DC Balancing Supports
3 DescriptionAC-Coupled Data Transmission
The DS90URxxx-Q1 chipset• Capableto Drive upto10 Meters Shielded parallel bus intoa fully transparentTwisted-Pair Cable LinkII LVDS serial stream• No Reference Clock Required (Deserializer) information. This chipsetis Meets ISO 10605 ESD– Greater than8kV HBM graphical datato displays requiring
RGB666+ HS, VS, DE+ESD Structure
purpose data channels. This• Hot Plug Support simplifies transferringa 24-bit bus over• EMI Reduction– Serializer Accepts Spread and cableby eliminating the skew problemsSpectrum Input; Data Randomization and parallel data and clock paths. TheShuffling on Serial Link; Deserializer Provides system cost by narrowing data paths
Adjustable PTO (Progressive Turnon) LVCMOS reduce PCB layers, cable width, and
and pins.Outputs @Speed BIST (Built-In Self-Test)to Validate The DS90URxxx-Q1 incorporatesLVDS Transmission Path signaling on the high-speed
providesa low-power and• Individual Power-Down Controls for Both
reliably transferring dataTransmitter and Receiver path. By optimizing the Serializer• Power Supply Range 3.3V ±10% the operating frequency• 48-Pin TQFP Package for Transmitter and 64-Pin reduced.
TQFP Package for Receiver
Device Information(1)• Temperature Range: –40°Cto 105°C• Backward-Compatible Mode WithDS90C241/DS90C124
(1) Forall available packages, see
the endofthe data sheet.
Applications Diagram Block Diagram
