DS90LV110TMTC ,1 to 10 LVDS Data/Clock DistributorFeaturesn Low jitter 800 Mbps fully differential data pathDS90LV110 isa1to10 data/clock distributor ..
DS90LV804TSQ ,4-Channel 800 Mbps LVDS Buffer/Repeater 32-WQFN -40 to 85features both an internal input and output (source)23• 800 Mbps Data Rate per Channeltermination to ..
DS90LV804TSQ ,4-Channel 800 Mbps LVDS Buffer/Repeater 32-WQFN -40 to 85Maximum RatingsSupply Voltage (V )−0.3V to +4.0VDDCMOS Input Voltage (EN)−0.3V to (V +0.3V)DD(2)LVD ..
DS90LV804TSQX/NOPB ,4-Channel 800 Mbps LVDS Buffer/Repeater 32-WQFN -40 to 85Electrical CharacteristicsOver recommended operating supply and temperature ranges unless other spe ..
DS90UR124IVS/NOPB ,5-43MHz DC-Balanced 24-Bit FPD-Link II Deserializer 64-TQFP -40 to 105Features 2 Applications1• Supports Displays With 18-Bit Color Depth • Automotive Central Informatio ..
DS90UR124IVSX , 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset
DS90LV110TMTC
1 to 10 LVDS Data/Clock Distributor
DS90LV110T to 10 L VDS Data/Clock Distributor
General DescriptionDS90LV110 isa1to10 data/clock distributor utilizing LVDS
(Low Voltage Differential Signaling) technology for low
power, high speed operation. Data paths are fully differential
from inputto outputfor low noise generation and low pulse
width distortion. The design allows connectionof1 inputto
all10 outputs. LVDSI/O enable high speed data transmis-
sionfor point-to-point interconnects. This device canbe useda high speed differential1to10 signal distribution/ fanout
replacing multi-drop bus applicationsfor higher speed links
with improved signal quality.It can alsobe usedfor clock
distributionupto 400MHz.
The DS90LV110 accepts LVDS signal levels, LVPECL levels
directlyor PECL with attenuation networks.
The LVDS outputs canbe put into TRI-STATEby useof the
enable pin.
For more details, please refertothe Application Information
sectionof this datasheet.
Features Low jitter 800 Mbps fully differential data path 145ps (typ)of pk-pk jitter with PRBS=223−1 data
patternat 800 Mbps Single +3.3V Supply Less than 413 mW (typ) total power dissipation Balanced output impedance Output channel-to-channel skewis 35ps (typ) Differential output voltage (VOD)is 320mV (typ) with
100Ω termination load. LVDS receiver inputs accept LVPECL signals Fast propagation delayof 2.8ns (typ) Receiver input threshold< ±100 mV28 lead TSSOP package Conformsto ANSI/TIA/EIA-644 LVDS standard
Connection DiagramOrder Number DS90LV110TMTC
SeeNS Package Number MTC28
Block Diagram
July 2001
VDS
Data/Clock
Distributor
