DS90LV110ATMTX ,1 to 10 LVDS Data/Clock Distributor with FailsafeElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90LV110TMTC ,1 to 10 LVDS Data/Clock DistributorFeaturesn Low jitter 800 Mbps fully differential data pathDS90LV110 isa1to10 data/clock distributor ..
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DS90LV110ATMT-DS90LV110ATMTX
1 to 10 LVDS Data/Clock Distributor with Failsafe
DS90LV110AT to 10 L VDS Data/Clock Distributor with Failsafe
General DescriptionDS90LV110A isa1to10 data/clock distributor utilizing LVDS
(Low Voltage Differential Signaling) technology for low
power, high speed operation. Data paths are fully differential
from inputto outputfor low noise generation and low pulse
width distortion. The design allows connectionof1 inputto
all10 outputs. LVDSI/O enable high speed data transmis-
sionfor point-to-point interconnects. This device canbe useda high speed differential1to10 signal distribution/ fanout
replacing multi-drop bus applicationsfor higher speed links
with improved signal quality.It can alsobe usedfor clock
distributionupto 200MHz.
The DS90LV110A accepts LVDS signal levels, LVPECL lev-
els directlyor PECL with attenuation networks.
The LVDS outputs canbe put into TRI-STATEby useof the
enable pin.
For more details, please referto the Application Information
sectionof this datasheet.
Features Low jitter 400 Mbps fully differential data path 145ps (typ)of pk-pk jitter with PRBS=223−1 data
patternat 400 Mbps Single +3.3V Supply Balanced output impedance Output channel-to-channel skewis 35ps (typ) Differential output voltage (VOD)is 320mV (typ) with
100Ω termination load. LVDS receiver inputs accept LVPECL signals LVDS input failsafe Fast propagation delayof 2.8ns (typ) Receiver open, shorted, and terminated input failsafe28 lead TSSOP package Conformsto ANSI/TIA/EIA-644 LVDS standard
Connection DiagramOrder Number DS90LV110ATMT
SeeNS Package Number MTC28
Block Diagram
October 2004
DS90L
10A
VDS
Data/Clock
Distributor
with
Failsafe
