DS90LV048ATMTCX ,3V LVDS Quad CMOS Differential Line ReceiverDS90LV048A 3V LVDS Quad CMOS Differential Line ReceiverMay 2001DS90LV048A3V LVDS Quad CMOS Differen ..
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DS90LV048ATMTC-DS90LV048ATMTC.-DS90LV048ATMTCX-DS90LV048ATMX
3V LVDS Quad CMOS Differential Line Receiver
DS90LV048A LVDS Quad CMOS Differential Line Receiver
General DescriptionThe DS90LV048Aisa quad CMOS flow-through differential
line receiver designed for applications requiring ultra low
power dissipation and high data rates. The deviceis de-
signedto support data ratesin excessof 400 Mbps (200
MHz) utilizing Low Voltage Differential Signaling (LVDS)
technology.
The DS90LV048A accepts low voltage (350 mV typical) dif-
ferential input signals and translates themto 3V CMOS
output levels. The receiver supportsa TRI-STATE® function
that maybe usedto multiplex outputs. The receiver also
supports open, shorted and terminated (100Ω) input fail-
safe. The receiver outputwillbe HIGHforall fail-safe condi-
tions. The DS90LV048A hasa flow-through pinoutfor easy
PCB layout.
TheEN and EN* inputsare ANDed together and controlthe
TRI-STATE outputs. The enables are commontoall four
receivers. The DS90LV048A and companion LVDS line
driver (eg. DS90LV047A) providea new alternativeto high
power PECL/ECL devicesfor high speed point-to-point inter-
face applications.
Features >400 Mbps (200 MHz) switching rates Flow-through pinout simplifies PCB layout 150ps channel-to-channel skew (typical) 100ps differential skew (typical) 2.7ns maximum propagation delay 3.3V power supply design High impedance LVDS inputson power down Low Power design (40mW 3.3V static) Interoperable with existing5V LVDS drivers Accepts small swing (350 mV typical) differential signal
levels Supports open, short and terminated input fail-safe0Vto −100mV threshold region Conformsto ANSI/TIA/EIA-644 Standard Industrial temperature operating range (-40˚Cto +85˚C) Availablein SOIC and TSSOP package
Connection Diagram
Dual-in-LineOrder Number DS90LV048ATM, DS90LV048ATMTC
SeeNS Package Number M16A, MTC16
Functional Diagram
Truth Table
ENABLES INPUTS OUTPUT EN* RIN+ −RIN− ROUT Lor Open VID≥0V H
VID≤ −0.1V L
Full Fail-safe
OPEN/SHORT Terminated
May 2001
DS90L
V048A
VDS
Quad
CMOS
Differential
Line
Receiver
