DS90LV032ATM NOPB ,3V LVDS Quad CMOS Differential Line Receiver 16-SOIC -40 to 85 SNLS011D–JULY 1999–REVISED AUGUST 20165 Pin Configuration and FunctionsD or PW Package16-Pin SOIC ..
DS90LV032ATMTC ,3V LVDS Quad CMOS Differential Line Receiverapplications. In addition, the DS90LV032A provides power-off high impedance LVDS inputs. This featu ..
DS90LV032ATMTCX ,3V LVDS Quad CMOS Differential Line Receiverapplications.Connection Diagram Functional DiagramDual-in-LineDS100067-1Order Number DS90LV032ATMor ..
DS90LV032ATMX ,3V LVDS Quad CMOS Differential Line ReceiverFeatures- High impedance LVDS inputs with power-off - Accepts small swing (330 mV) differential sig ..
DS90LV032ATMX NOPB ,3V LVDS Quad CMOS Differential Line Receiver 16-SOIC -40 to 85Features 3 DescriptionThe DS90LV032A is a quad CMOS differential line1• >400 Mbps (200 MHz) Switchi ..
DS90LV032ATMX/NOPB ,3V LVDS Quad CMOS Differential Line Receiver 16-SOIC -40 to 85Block Diagram... 104 Revision HistoryNOTE: Page numbers for previous revisions may differ from page ..
DS90LV032ATM NOPB-DS90LV032ATMX NOPB-DS90LV032ATMX/NOPB
3V LVDS Quad CMOS Differential Line Receiver 16-SOIC -40 to 85
ROUT1ROUT2
ROUT3
RIN4-
RIN3+
RIN3-
RIN2+
RIN2-
RIN1+
RIN1-
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DS90LV032ASNLS011D –JULY 1999–REVISED AUGUST 2016
DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver Features >400 Mbps (200 MHz) Switching Rates 0.1-ns Channel-to-Channel Skew (Typical) 0.1-ns Differential Skew (Typical) 3.3-ns Maximum Propagation Delay 3.3-V Power Supply Design Power Down High Impedance on LVDS Inputs Low Power Design (40 mWat 3.3V Static) Interoperable With Existing 5-V LVDS Networks Accepts Small Swing (350 mV Typical) VID Supports Open, Short, and Terminated Input Fail-
Safe Compatible With ANSI/TIA/EIA-644 Industrial Temperature Operating Range (–40°C 85°C) Availablein SOIC and TSSOP Packaging
Applications Building And Factory Automation Grid Infrastructure
DescriptionThe DS90LV032Aisa quad CMOS differential
receiver designed for applications requiring ultra-low
power dissipation and high data rates. The device
designedto support data ratesin excessof 400
(200 MHz) using Low Voltage Differential Signaling
(LVDS) technology.
The DS90LV032A accepts low voltage (350
typical) differential input signals and translates 3-V CMOS output levels. The receiver supports
TRI-STATE function that may be usedto multiplex
outputs. The receiver also supports open, shorted,
and terminated (100 Ω) input Fail-safe. The receiver
outputis HIGH forall fail-safe conditions.
The DS90LV032A and companion LVDS line
(for example, DS90LV031A) provide a
alternativeto high power PECLor ECL devices
high speed point-to-point interface applications.
Device Information(1)(1) Forall available packages, see the orderable addendum
the endofthe data sheet.
Block Diagram
