DS90LV032 ,3V LVDS Quad CMOS Differential Line Receiverapplications requiring ultra low power dissipa- 100 Mbps (50 MHz) switching ratestion and high data ..
DS90LV032A ,3V LVDS Quad CMOS Differential Line ReceiverElectrical CharacteristicsOver Supply Voltage and Operating Temperature ranges, unless otherwise sp ..
DS90LV032ATM ,3V LVDS Quad CMOS Differential Line ReceiverMICROCIRCUIT DATA SHEETOriginal Creation Date: 2/21/00MNDS90LV032A-X REV 0D0Last Update Date: 11/10 ..
DS90LV032ATM NOPB ,3V LVDS Quad CMOS Differential Line Receiver 16-SOIC -40 to 85 SNLS011D–JULY 1999–REVISED AUGUST 20165 Pin Configuration and FunctionsD or PW Package16-Pin SOIC ..
DS90LV032ATMTC ,3V LVDS Quad CMOS Differential Line Receiverapplications. In addition, the DS90LV032A provides power-off high impedance LVDS inputs. This featu ..
DS90LV032ATMTCX ,3V LVDS Quad CMOS Differential Line Receiverapplications.Connection Diagram Functional DiagramDual-in-LineDS100067-1Order Number DS90LV032ATMor ..
DS90LV032
3V LVDS Quad CMOS Differential Line Receiver
TL/F/12624
DS90LV032
LVDS
Quad
CMOS
Differential
Line
Receiver
December 1996
DS90LV032 LVDS Quad CMOS Differential Line Receiver
General Description
The DS90LV032isa quad CMOS differentialline receiver
designedfor applications requiring ultralow power dissipa-
tionand high data rates.The deviceis designedto support
data ratesin excessof 100 Mbps(50 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.
The DS90LV032 acceptslow voltage (350mVtyp) differen-
tial input signals and translates themto3V CMOS output
levels. The receiver supportsa TRI-STATEÉ functionthat
maybe usedto multiplex outputs. The receiver also sup-
ports OPEN, shortedand terminated (100X) input Failsafe.
The receiver outputwillbe Highforall failsafe conditions.
The DS90LV032 and companion line driver (DS90LV031)
providea new alternativeto high power psuedo-ECL devic-for high speed pointto point interface applications.
Features 3.3V power supply designl100 Mbps(50 MHz) switching rates Accepts small swing (350mVtyp) differential signal
levels Ultralow power dissipation 800ps maximum differential skew (3.3V, 25§C) High impedance during poweroff Industrial operating temperature range
(b40§Cto a85§C) Availablein surface mount packaging (SOIC)Pin compatible with DS26C32A, MB570 (PECL), 41LF
(PECL),and DS90C032 (5V) Supports OPEN, shortand terminated input failsafe Compatible with IEEE 1596.3SCI LVDS standard Compatible with TIA/EIA-644 LVDS standard
Connection Diagram
Dual-In-Line
TL/F/12624–1
OrderNumber
DS90LV032TM
See NSPackageNumberM16A
Functional Diagram and Truth Table
TL/F/12624–2
RECEIVER
ENABLES INPUTS OUTPUT EN* RINab RINb ROUT X Z
All othercombinations VIDt 0.1V H ENABLE inputs VIDs b0.1V L
Full Failsafe
OPEN/SHORT H Terminated
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1996National SemiconductorCorporation RRD-B30M126/Printed inU.S.A. http://
