DS90LV001TMX ,3.3V LVDS-LVDS BufferFeaturesthe distance between the transmission line and the untermi-nated receivers on individual ca ..
DS90LV011ATMF ,Single High Speed Differential DriverFeaturesn Conforms to TIA/EIA-644-A StandardThe DS90LV011A is a single LVDS driver device optimized ..
DS90LV011ATMFX ,Single High Speed Differential DriverDS90LV011A 3V LVDS Single High Speed Differential DriverMay 2002DS90LV011A3V LVDS Single High Speed ..
DS90LV012ATMF ,3V LVDS Single CMOS Differential Line ReceiverElectrical CharacteristicsOver Supply Voltage and Operating Temperature ranges, unless otherwise sp ..
DS90LV012ATMF/NOPB ,3V LVDS Single CMOS Differential Line Receiver 5-SOT-23 -40 to 85Figure 2. Top ViewSee Package Number NGK0008AFunctional DiagramFigure 3. DS90LV012AFigure 4. DS90LT ..
DS90LV012ATMFX/NOPB ,3V LVDS Single CMOS Differential Line Receiver 5-SOT-23 -40 to 85FEATURES DESCRIPTIONThe DS90LV012A and DS90LT012A are single2• Compatible with ANSI TIA/EIA-644-A S ..
DS90LV001TLD-DS90LV001TM-DS90LV001TMX
3.3V LVDS-LVDS Buffer
DS90LV001
3.3V LVDS-LVDS Buffer
General DescriptionThe DS90LV001 LVDS-LVDS Buffer takesan LVDS input
signal and providesan LVDS output signal.In many large
systems, signals are distributed across backplanes, and onethe limiting factorsfor system speedisthe ’stub length’or
the distance between the transmission line andthe untermi-
nated receiverson individual cards. Althoughitis generally
recognized that this distance shouldbeas shortas possible maximize system performance, real-world packaging con-
cerns often makeit difficultto makethe stubsas shortasthe
designer would like.
The DS90LV001, availableinthe LLP (Leadless Leadframe
Package) package,will allowthe receivertobe placed very
closetothe main transmission line, thus improving system
performance. wide input dynamic range will allow the DS90LV001to
receive differential signals from LVPECLas wellas LVDS
sources. This will allow the deviceto alsofillthe roleofan
LVPECL-LVDS translator. output enable pinis provided, which allows the userto
placethe LVDS outputin TRI-STATE.
The DS90LV001is offeredin two package options,an8pin
LLP and SOIC.
Features Single +3.3V Supply LVDS receiver inputs accept LVPECL signals TRI-STATE outputs Receiver input threshold< ±100 mV Fast propagation delayof 1.4ns (typ) Low jitter 800 Mbps fully differential data path 100ps (typ)of pk-pk jitter with PRBS=223−1 data
patternat 800 Mbps Compatible with ANSI/TIA/EIA-644-A LVDS standard8pin SOIC and space saving (70%) LLP package Industrial Temperature Range
Connection Diagram
Block Diagram
Top ViewDS101338-5
Order Number DS90LV001TM, DS90LV001TLD
See NS Package Number M08A, LDA08ADS101338-2
April 2001
DS90L
V001
3.3V
VDS-L
VDS
Buffer
