DS90CR484AVJD/NOPB ,48-Bit LVDS Channel Link SER/DESFEATUREScable reduction. Long distance parallel single-ended2• Up to 5.38 Gbits/sec Bandwidthbuses ..
DS90CR485VS ,133MHz LVDS 48-bit Channel Link Serializer
DS90CR485VS ,133MHz LVDS 48-bit Channel Link Serializer
DS90CR485VS/NOPB ,133MHz LVDS 48-bit Channel Link Serializer 100-TQFP -10 to 70Electrical Characteristics (continued)Over recommended operating supply and temperature ranges unle ..
DS90CR486VS ,DeserializerElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CR486VS/NOPB ,Deserializer 100-TQFP -10 to 70FEATURESgenerations of Channel Link devices and offers2• Up to 6.384 Gbps Throughputhigher bandwidt ..
DS90CR484AVJD/NOPB
48-Bit LVDS Channel Link SER/DES
DS90CR483A, DS90CR484A
www.ti.com SNLS291A–APRIL 2008–REVISED APRIL 2013
DS90CR483A/ DS90CR484A 48-Bit LVDS Channel Link SER/DES– 33- 112 MHz
Checkfor Samples: DS90CR483A, DS90CR484AThe multiplexingof data lines providesa substantial
1FEATUREScable reduction. Long distance parallel single-ended
Upto 5.38 Gbits/sec Bandwidth buses typically requirea ground wire per active signal
33 MHzto 112 MHz Input Clock Support (and have very limited noise rejection capability).
Thus, fora 48-bit wide data and one clock, upto 98
• LVDS SER/DES Reduces Cable and Connector conductors are required. With this Channel Link
Size chipsetas fewas19 conductors(8 data pairs,1 clock
• Pre-emphasis Reduces Cable Loading Effects pair anda minimumof one ground) are needed. This
DC Balance Data Transmission Providedby provides an 80% reduction in cable width, which
Transmitter Reduces ISI Distortion providesa system cost savings, reduces connector
physical size and cost, and reduces shielding
• Cable Deskewof +/−1 LVDS Data Bit Time (up requirements dueto the cables' smaller form factor.
to80 MHz Clock Rate)The 48 CMOS/TTL inputs can supporta varietyof
• 5V Tolerant TxIN and Control Input Pins signal combinations. For example,6 8-bit wordsor5
• Flow Through Pinout for Easy PCB Design 9-bit (byte+ parity) and3 controls.
• +3.3V Supply Voltage The DS90CR483A/DS90CR484A chipsetis improved
• Transmitter Rejects Cycle-to-Cycle Jitter over prior generationsof Channel Link devices and
• Conformsto ANSI/TIA/EIA-644-1995 LVDS offers higher bandwidth support and longer cable
Standard drive with three areasof enhancement. To increase
bandwidth, the maximum clock rateis increasedto
• Both Devices are Availablein 100 Lead TQFP 112 MHz and 8 serialized LVDS outputs are
Package provided. Cable drive is enhanced witha user
selectable pre-emphasis feature that provides
DESCRIPTION additional output current during transitions toThe DS90CR483A transmitter converts 48 bits of counteract cable loading effects. Optional DCCMOS/TTL data into eight LVDS (Low Voltage balancing ona cycle-to-cycle basis,is also providedDifferential Signaling) data streams.A phase-locked to reduce ISI (Inter-Symbol Interference). With pre-transmit clockis transmittedin parallel with the data emphasis and DC balancing,a low distortion eye-streams overa ninth LVDS link. Every cycleof the patternis providedat the receiver endof the cable.Atransmit clock 48 bitsof input data are sampled and cable deskew capability has been addedto deskewtransmitted. The DS90CR484A receiver converts the long cablesof pair-to-pair skewof upto +/−1 LVDSLVDS data streams back into 48 bitsof CMOS/TTL databit time (upto 80 MHz Clock Rate). These three frequencyof 112MHz, 48 enhancements allow cables 5+ metersin lengthto bea rateof 672Mbps driven. Using 112MHz clock, the The chipsetisan ideal meansto solve EMI and cable size problems associated with wide, high speed TTL
For more details, please refer to the Applications
Information section
