DS90CR481VJD/NOPB ,48-Bit LVDS Channel Link SerializerFEATUREScable reduction. Long distance parallel single-ended2• 3.168 Gbits/sec Bandwidth with 66 MH ..
DS90CR482VS ,48-Bit LVDS Channel Link DeserializerFeaturesreduction. Long distance parallel single-ended buses typi-n 3.168 Gbits/sec bandwidth with ..
DS90CR482VS/NOPB ,48-Bit LVDS Channel Link Deserializer
DS90CR484AVJD/NOPB ,48-Bit LVDS Channel Link SER/DESFEATUREScable reduction. Long distance parallel single-ended2• Up to 5.38 Gbits/sec Bandwidthbuses ..
DS90CR485VS ,133MHz LVDS 48-bit Channel Link Serializer
DS90CR485VS ,133MHz LVDS 48-bit Channel Link Serializer
DS90CR481VJD/NOPB
48-Bit LVDS Channel Link Serializer
DS90CR481, DS90CR482
www.ti.com SNLS137D –NOVEMBER 2000–REVISED APRIL 2013
DS90CR481/ DS90CR482 48-Bit LVDS Channel Link SER/DES− 65- 112 MHz
Checkfor Samples: DS90CR481, DS90CR482The multiplexingof data lines providesa substantial
1FEATUREScable reduction. Long distance parallel single-ended
3.168 Gbits/sec Bandwidth with66 MHz Clock buses typically requirea ground wire per active signal
5.376 Gbits/sec Bandwidth with 112 MHz Clock (and have very limited noise rejection capability).
Thus, fora 48-bit wide data and one clock, upto 98
• 65- 112 MHz Input Clock Support conductors are required. With this Channel Link
• LVDS SER/DES Reduces Cable and Connector chipsetas fewas19 conductors(8 data pairs,1 clock
Size pair anda minimumof one ground) are needed. This
Pre-Emphasis Reduces Cable Loading Effects provides an 80% reduction in cable width, which
providesa system cost savings, reduces connector
• Optional DC Balance Encoding Reduces ISI physical size and cost, and reduces shielding
Distortion requirements dueto the cables' smaller form factor.
• Cable Deskewof +/−1 LVDS Data Bit Time (upThe 48 CMOS/TTL inputs can supporta varietyof
to80 MHz Clock Rate) signal combinations. For example,6 8-bit wordsor5
• 5V Tolerant TxIN and Control Input Pins 9-bit (byte+ parity) and3 controls.
• Flow Through Pinout for Easy PCB Design The DS90CR481/DS90CR482 chipsetis improved
• +3.3V Supply Voltage over prior generationsof Channel Link devices and
• Transmitter Rejects Cycle-to-Cycle Jitter offers higher bandwidth support and longer cable
drive with three areasof enhancement. To increase
• Conformsto ANSI/TIA/EIA-644-1995 LVDS bandwidth, the maximum clock rateis increasedto
Standard 112 MHz and 8 serialized LVDS outputs are
provided. Cable drive is enhanced witha user
DESCRIPTION selectable pre-emphasis feature that providesThe DS90CR481 transmitter converts 48 bits of additional output current during transitions toCMOS/TTL data into eight LVDS (Low Voltage counteract cable loading effects. Optional DCDifferential Signaling) data streams.A phase-locked balancing ona cycle-to-cycle basis,is also providedtransmit clockis transmittedin parallel with the data to reduce ISI (Inter-Symbol Interference). With pre-streams overa ninth LVDS link. Every cycleof the emphasis and DC balancing,a low distortion eye-transmit clock 48 bitsof input data are sampled and patternis providedat the receiver endof the cable.Atransmitted. The DS90CR482 receiver converts the cable deskew capability has been addedto deskewLVDS data streams back into 48 bits of long cablesof pair-to-pair skewof upto +/−1 LVDSLVCMOS/TTL data.Ata transmit clock frequencyof databit time (upto 80 MHz Clock Rate). These three data are transmittedata rate enhancements allow cables 5+ metersin lengthto be Usinga 112MHz driven. throughput is 5.38Gbit/s
The chipsetisan ideal meansto solve EMI and cable transmit frequency of
size problems associated with wide, high speed TTL data are transmittedata rate 66MHz
