DS90CR286MTD ,+3.3V Rising Edge Data Strobe LVDS 28-Bit ChannelGeneral Descriptionsignal combinations. For example, seven 4-bit nibbles orThe DS90CR285 transmitte ..
DS90CR286MTDX ,+3.3V Rising Edge Data Strobe LVDS 28-Bit ChannelFeaturested in parallel with the data streams over a fifth LVDS link.n Single +3.3V supplyEvery cyc ..
DS90CR287MTDX ,+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link Transmitter
DS90CR287MTDX ,+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link Transmitter
DS90CR288AMTD/NOPB ,+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link ReceiverElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CR288MTD ,+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link ReceiverFeaturesn 20 to 75 MHz shift clock supportThe DS90CR287 (see DS90CR287/288A datasheet) trans-mitter ..
DS90CR285MTD-DS90CR286MTD-DS90CR286MTDX
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel
DS90CR285/DS90CR286
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel
Link-66 MHz
General DescriptionThe DS90CR285 transmitter converts28 bitsof LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signal-
ing) data streams.A phase-locked transmit clockis transmit-
tedin parallel with the data streams overa fifth LVDS link.
Every cycleof the transmit clock28 bitsof input data are
sampled and transmitted. The DS90CR286 receiver con-
vertsthe LVDS data streams back into28 bitsof LVCMOS/
LVTTL data.Ata transmit clock frequencyof66 MHz,28 bits TTL dataare transmittedata rateof 462 Mbps per LVDS
data channel. Usinga66 MHz clock,the data throughputis
1.848 Gbit/s (231 Mbytes/s).
The multiplexingof the data lines providesa substantial
cable reduction. Long distance parallel single-ended buses
typically requirea ground wire per active signal (and have
very limited noise rejection capability).Thus,fora 28-bitwide
data and one clock,upto58 conductors are required. With
the Channel Link chipsetas fewas11 conductors(4 data
pairs,1 clock pair anda minimumof one ground) are
needed. This providesa 80% reductionin required cable
width, which providesa system cost savings, reduces con-
nector physical size and cost, and reduces shielding require-
ments dueto the cables’ smaller form factor.
The28 LVCMOS/LVTTL inputs can supporta varietyof
signal combinations. For example, seven 4-bit nibblesor
three 9-bit (byte+ parity) and1 control.
Features Single +3.3V supply Chipset (Tx+ Rx) power consumption <250 mW (typ) Power-down mode (<0.5 mW total) Upto 231 Megabytes/sec bandwidth Upto 1.848 Gbps data throughput Narrow bus reduces cable size 290 mV swing LVDS devicesfor low EMI +1V common mode range (around +1.2V) PLL requiresno external components Both devices are offeredina Low profile 56-lead
TSSOP package Rising edge data strobe Compatible with TIA/EIA-644 LVDS standard ESD Rating> 7kV Operating Temperature: −40˚Cto +85˚C
Block Diagrams
DS90CR285 DS90CR286Order Number DS90CR285MTD
SeeNS Package Number MTD56
Order Number DS90CR286MTD
SeeNS Package Number MTD56
July 2004
DS90CR285/DS90CR286
+3.3V
Rising
Edge
Data
Strobe
VDS
28-Bit
Channel
Link-66
MHz
