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DS90CR218AMTDX/NOPB
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link Receiver
DS90CR218A
www.ti.com SNLS054D –NOVEMBER 1999–REVISED APRIL 2013
DS90CR218A +3.3V Rising Edge Data Strobe LVDS
21-Bit Channel Link- 12 MHzto 85 MHz
Checkfor Samples: DS90CR218A
1FEATURES
DESCRIPTION• 12to85 MHz Shift Clock Support The DS90CR218A receiver deserializes three input
• 50% Duty Cycle on Receiver Output Clock LVDS data streams into21 bitsof CMOS/TTL output
• Low Power Consumption data. When operatingat the maximum input clock
rateof 85 Mhz, the LVDS datais receivedat 595
• ±1V Common-mode Range (Around +1.2V)Mbps per data channel fora total data throughputof
• Narrow Bus Reduces Cable Size and Cost 1.785 Gbit/sec (233 Mbytes/sec).
• Upto 1.785 Gbps Throughput The narrow bus and LVDS signalling of the
• Upto 223 Mbytes/sec Bandwidth DS90CR218Ais an ideal meansto solve EMI and
• 345 mV (typ) Swing LVDS Devices for Low EMI cable size problems associated with wide, high-speed
TTL interfaces.
• PLL Requires No External Components Rising Edge Data Strobe Compatible with TIA/EIA-644 LVDS Standard Low Profile 48-Lead TSSOP Package
Block Diagram
Figure1. DS90CR218A Top View
See Package Number DGG-48 (TSSOP)