DS90CF564MTDX/NOPB ,LVDS 18-Bit Color Flat Panel Display (FPD) LinkElectrical Characteristics (continued)Over recommended operating supply and temperature ranges unle ..
DS90CF581MTD ,LVDS Transmitter 24-Bit Color Flat Panel Display (FPD) LinkElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CF581MTDX ,LVDS Transmitter 24-Bit Color Flat Panel Display (FPD) LinkFeaturesn Up to 140 Megabyte/sec BandwidthThe DS90CF581 transmitter converts 28 bits of CMOS/TTLdat ..
DS90CF582MTD ,LVDS 24-Bit Color Flat Panel Display (FPD) LinkDS90CF581/DS90CF582LVDS24-BitColorFlatPanelDisplay(FPD)LinkApril1996DS90CF581/DS90CF582LVDS24-BitCo ..
DS90CF582MTD ,LVDS 24-Bit Color Flat Panel Display (FPD) LinkFeaturesYUp to 140 Megabyte/sec BandwidthThe DS90CF581 transmitter converts 28 bits of CMOS/TTLYdat ..
DS90CF583MTD ,LVDS 24-Bit Color Flat Panel Display (FPD) LinkBlock DiagramsDS012616-24 DS012616-1Order Number DS90CF583MTD Order Number DS90CF584MTDSee NS Packa ..
DS90CF564MTDX/NOPB
LVDS 18-Bit Color Flat Panel Display (FPD) Link
DS90CF563, DS90CF564
www.ti.com SNLS107E –JULY 1997–REVISED APRIL 2013
DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display (FPD) Link- 65 MHz
Checkfor Samples: DS90CF563, DS90CF564
1FEATURES DESCRIPTIONThe DS90CF563 transmitter converts 21 bits of
20to65 MHz Shift Clk Support CMOS/TTL data into three LVDS (Low Voltage
• Upto 171 Mbytes/s Bandwidth Differential Signaling) data streams.A phase-locked
Cable Sizeis Reducedto Save Cost transmit clockis transmittedin parallel with the data
streams overa fourth LVDS link. Every cycleof the
• 290 mV Swing LVDS Devices for Low EMI transmit clock 21 bitsof input data are sampled and
• Low Power CMOS Design(< 550 mW typ) transmitted. The DS90CF564 receiver converts the
• Power-down Mode Saves Power(< 0.25 mW) LVDS data streams back into 21 bitsof CMOS/TTL
data.Ata transmit clock frequencyof65 MHz,18 bits
• PLL Requires No External Components of RGB data and3 bitsof LCD timing and control
• Low Profile 48-Lead TSSOP Package data (FPLINE, FPFRAME, DRDY) are transmittedat
• Falling Edge Data Strobe a rateof 455 Mbps per LVDS data channel. Usinga MHz clock, the data throughputis 171 Mbytes per
• Compatible with TIA/EIA-644 LVDS Standardsecond. These devices are offered with falling edge
• Single Pixel Per Clock XGA (1024x 768) data strobes for convenient interface witha varietyof
• Supports VGA, SVGA, XGA and Higher graphics and LCD panel controllers.
1.3 Gbps Throughput This chipsetis an ideal meansto solve EMI and
cable size problems associated with wide, high speed
TTL interfaces.
Block Diagram Figure available. See Package
