DS90CF563MTD ,LVDS 18-Bit Color Flat Panel Display (FPD) LinkBlock DiagramsDS90CF563DS90CF564DS012615-2DS012615-1Order Number DS90CF563MTDOrder Number DS90CF564 ..
DS90CF564MTD ,LVDS 18-Bit Color Flat Panel Display (FPD) LinkFeaturesn 20 to 65 MHz shift clk supportThe DS90CF563 transmitter converts 21 bits of CMOS/TTLdata ..
DS90CF564MTD. ,LVDS 18-Bit Color Flat Panel Display (FPD) LinkBlock Diagrams (Continued)DS012615-3 2Absolute Maximum Ratings (Note 1) DS90CF563 1.98WDS90CF564 1. ..
DS90CF564MTDX ,LVDS 18-Bit Color Flat Panel Display (FPD) LinkFeaturesn 20 to 65 MHz shift clk supportThe DS90CF563 transmitter converts 21 bits of CMOS/TTLdata ..
DS90CF564MTDX/NOPB ,LVDS 18-Bit Color Flat Panel Display (FPD) LinkElectrical Characteristics (continued)Over recommended operating supply and temperature ranges unle ..
DS90CF581MTD ,LVDS Transmitter 24-Bit Color Flat Panel Display (FPD) LinkElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CF563MTD-DS90CF564MTD-DS90CF564MTD.-DS90CF564MTDX
LVDS 18-Bit Color Flat Panel Display (FPD) Link
DS90CF563/DS90CF564
LVDS 18-Bit Color Flat Panel Display (FPD) Link— MHz
General DescriptionThe DS90CF563 transmitter converts21bitsof CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams.Aphase-locked transmit clock istransmittedin
parallelwiththe data streams overa fourth LVDSlink. Every
cycleofthe transmit clock21bitsof input dataare sampled
and transmitted. The DS90CF564 receiver convertsthe
LVDS data streams backinto21bitsof CMOS/TTL data.At transmit clock frequencyof65 MHz,18bitsof RGB data
and3 bitsof LCD timing and control data (FPLINE,
FPFRAME,DRDY)are transmittedat arateof455 Mbpsper
LVDS data channel. Using a65 MHz clock,the data through-
putis 171 Mbytesper second. These devicesare offered
with falling edge data strobesfor convenient interfacewitha
varietyof graphicsand LCD panel controllers.
This chipsetisan ideal meansto solve EMIand cable size
problems associated with wide, high speed TTL interfaces.
Features20to65 MHz shiftclk supportUpto171 Mbytes/s bandwidth Cable sizeis reducedto save cost 290mV swing LVDS devicesforlowEMI Low power CMOS design(<550 mWtyp) Power-down mode saves power(< 0.25 mW) PLL requiresno external components Low profile 48-lead TSSOP package Falling edge data strobe Compatible with TIA/EIA-644 LVDS standard Single pixelper clock XGA (1024x 768) Supports VGA, SVGA, XGAand higher1.3 Gbps throughput
Block DiagramsTRI-STATE®isa registeredtrademark ofNationalSemiconductorCorporation.
DS90CF563DS012615-2
Order Number DS90CF563MTD
SeeNS Package Number MTD48
DS90CF564DS012615-1
Order Number DS90CF564MTD
SeeNS Package Number MTD48July 1997
DS90CF563/DS90CF564
VDS
18-Bit
Color
Flat
Panel
Display
(FPD)
Link
MHz 1998 National Semiconductor Corporation DS012615
