DS90CF386MTDX NOPB ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) LinkBlock Diagrams. 174 Revision HistoryNOTE: Page numbers for previous revisions may differ from page ..
DS90CF386MTDX/NOPB ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) LinkFeatures 3 DescriptionThe DS90CF386 receiver converts four LVDS (Low1• 20-MHz to 85-MHz Shift Clock ..
DS90CF386SLC ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-85 MHzBlock DiagramsDS90CF386 DS90CF3661010852710108528Order Number DS90CF386MTD or DS90CF386SLCOrder Num ..
DS90CF386SLCX/NOPB ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link SNLS055J–NOVEMBER 1999–REVISED MAY 20165 Pin Configuration and FunctionsDGG Package48-Pin TSSOPTop ..
DS90CF388AVJD ,Dual Pixel LVDS Display Interface / FPD-Link ReceiverBlock Diagrams10132001 2DS90C387A/DS90CF388ADS90C387A/DS90CF388AAbsolute Maximum Ratings (Note 1) P ..
DS90CF388VJD ,+3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGAGeneral Descriptionreduce EMI and shielding requirements. For more details,The DS90C387/DS90CF388 t ..
DS90CF386MTDX NOPB-DS90CF386MTDX/NOPB-DS90CF386SLCX/NOPB
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link
RxOUT[20:0]
LVDS Clock
LVDS Data
DS90CF366 21-Bit Rx
it
LVDS Cable or PCB Trace
18-Bit RGB Display Unit
100 Q
100 Q
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DS90CF366, DS90CF386SNLS055J –NOVEMBER 1999–REVISED MAY 2016
DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz Features 20-MHzto 85-MHz Shift Clock Support Rx Power Consumption <142 mW (Typical)at
85-MHz Grayscale Rx Power-Down Mode <1.44 mW (Maximum) ESD Rating>7 kV (HBM), >700V (EIAJ) Supports VGA, SVGA, XGA, and Single Pixel
SXGA PLL Requires No External Components Compatible With TIA/EIA-644 LVDS Standard Low Profile 56-Pinor 48-Pin TSSOP Package DS90CF386 Also Availableina 64-Pin, 0.8-mm,
Fine Pitch Ball Grid Array (NFBGA) Package
Applications Video Displays Printers and Imaging Digital Video Transport Machine Vision Open LDI-to-RGB Bridge
DescriptionThe DS90CF386 receiver converts four LVDS (Low
Voltage Differential Signaling) data streams back into
parallel28 bitsof LVCMOS data. Also availableis the
DS90CF366 receiver that converts three LVDS data
streams back into parallel 21 bitsof LVCMOS data.
The outputsof both receivers strobe on the falling
edge.A rising edgeor falling edge strobe transmitter
will interoperate witha falling edge strobe receiver
without any translation logic.
The receiver LVDS clock operates at rates from MHzto 85 MHz. The device phase-locksto the
input LVDS clock, samples the serial bit streamsat
the LVDS data lines, and converts them into parallel
output data.At an incoming clock rateof 85 MHz,
each LVDS input lineis running ata bit rate of
595 Mbps, resultingina maximum throughput of
2.38 Gbps for the DS90CF386 and 1.785 Gbps for
the DS90CF366.
The use of these serial link devicesis ideal for
solving EMI and cable size problems associated with
transmitting data over wide, high-speed parallel
LVCMOS interfaces. Both devices are offered in
TSSOP packages. The DS90CF386is also offeredin 64-pin, 0.8-mm, fine pitch ball grid array (NFBGA)
package which providesa 44% reductionin PCB
footprint comparedto the 56-pin TSSOP package.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Typical Application Block Diagram (DS90CF366)
