DS90CF364MTDX/NOPB ,+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) LinkFEATURES DESCRIPTIONThe DS90C363 transmitter converts 21 bits of23• 20 to 65 MHz shift clock suppor ..
DS90CF366MTD ,+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-85 MHzGeneral Descriptionproblems associated with wide, high speed TTL interfaces.The DS90CF386 receiver ..
DS90CF383AMTD ,+3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz [Life-time buy]Featuresn 20 to 65 MHz shift clock supportThe DS90C383A/DS90CF383A transmitter converts 28 bitsof C ..
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DS90CF383BMT ,+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHzBlock DiagramDS90C383B20098401Order Number DS90C383BMTSee NS Package Number MTD56®TRI-STATE is a re ..
DS90CF383BMTX/NOPB ,+3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz 56-TSSOP -10 to 70FEATURES DESCRIPTIONThe DS90CF383B transmitter converts 28 bits of23• No Special Start-up Sequence ..
DS90CF364MTD/NOPB-DS90CF364MTDX/NOPB
+3.3V Programmable LVDS Transmitter 18-Bit Flat Pane Display (FPD) Link 65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link 65 MHz
DS90C363, DS90CF364
www.ti.com SNLS123C –SEPTEMBER 1999–REVISED APRIL 2013
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link–65 MHz,
+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link–65 MHz
Checkfor Samples: DS90C363, DS90CF364
1FEATURES DESCRIPTIONThe DS90C363 transmitter converts 21 bits of
23• 20to65 MHz shift clock support CMOS/TTL data into three LVDS (Low Voltage
• Programmable Transmitter (DS90C363) strobe Differential Signaling) data streams.A phase-locked
select (Risingor Falling edge strobe) transmit clockis transmittedin parallel with the data
Single 3.3V supply streams overa fourth LVDS link. Every cycleof the
transmit clock 21 bitsof input data are sampled and
• Chipset (TX+ RX) power consumption< 250 transmitted. The DS90CF364 receiver converts the
mW (typ) LVDS data streams back into 21 bitsof CMOS/TTL
• Power-down mode(< 0.5 mW total) data.Ata transmit clock frequencyof65 MHz,18 bits
Single pixel per clock XGA (1024×768) ready of RGB data and3 bitsof LCD timing and control
data (FPLINE, FPFRAME, DRDY) are transmittedat
• Supports VGA, SVGA, XGA and higher a rateof 455 Mbps per LVDS data channel. Usinga
addressability 65 MHz clock, the data throughputis 170 Mbyte/sec.
• Upto 170 Megabyte/sec bandwidth The Transmitteris offered with programmable edge
Upto 1.3 Gbps throughput data strobes for convenient interface witha varietyof
graphics controllers. The Transmitter can be
• Narrow bus reduces cable size and cost programmed for Rising edge strobeor Falling edge
• 290 mV swing LVDS devices for low EMI strobe througha dedicated pin. A Rising edge
PLL requires no external components Transmitter will inter-operate witha Falling edge
Receiver (DS90CF364) without any translation logic.
• Low profile 48-lead TSSOP package Falling edge data strobe Receiver This chipsetis an ideal meansto solve EMI and
cable size problems associated with wide, high speed
• Compatible with TIA/EIA-644 LVDS standard TTL interfaces.
• ESD rating>7 kV Operating Temperature: −40°Cto +85°C
Block Diagrams
Figure1. Application
