DS90CF384AMTDX ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHzElectrical Characteristics (Continued)Note 1: “Absolute Maximum Ratings” are those values beyond wh ..
DS90CF384AMTDX/NOPB ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) LinkElectrical Characteristics (continued)Over recommended operating supply and temperature ranges unle ..
DS90CF384MTD ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHzFeaturesn 20 to 65 MHz shift clock supportThe DS90C383 transmitter converts 28 bits of LVCMOS/LVTTL ..
DS90CF384MTDX ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHzBlock DiagramsTypical ApplicationDS012887-2®TRI-STATE is a registered trademark of National Semicon ..
DS90CF386MTD ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-85 MHzFeaturessec bandwidth) back into parallel 28 bits of CMOS/TTLdatan 20 to 85 MHz shift clock support ..
DS90CF386MTDX ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-85 MHzElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CF364AMTD-DS90CF364AMTDX-DS90CF384AMTD-DS90CF384AMTD.-DS90CF384AMTDX
+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65 MHz
DS90CF384A/DS90CF364A
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD)
Link —65 MHz, +3.3V L VDS Receiver 18-Bit Flat Panel
Display (FPD) Link—65 MHz
General DescriptionThe DS90CF384A receiver converts the four LVDS data
streams (Upto1.8 Gbps throughputor 227 Megabytes/sec
bandwidth) back into parallel28 bitsof CMOS/TTL data (24
bitsof RGB and4 bitsof Hsync, Vsync,DE and CNTL).Also
availableisthe DS90CF364A that converts the three LVDS
data streams (Upto1.3 Gbps throughputor 170 Megabytes/
sec bandwidth) back into parallel21 bitsof CMOS/TTL data
(18 bitsof RGB and3 bitsof Hsync, Vsync and DE). Both
Receivers’ outputsare Falling edge strobe.A Rising edgeor
Falling edge strobe transmitter (DS90C383A/DS90C363A)
will interoperate witha Falling edge strobe Receiver without
any translation logic.
The DS90CF384A/ DS90CF364A devices are enhanced
over prior generation receivers and provideda wider data
valid timeonthe receiver output.
The DS90CF384Ais also offeredina64 ball, 0.8mm fine
pitch ball grid array (FBGA) package which providesa44%
reductionin PCB footprint comparedto the 56L TSSOP
package.
This chipsetisan ideal meansto solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features20to65 MHz shift clock support 50% duty cycleon receiver output clock Best–in–Class Set& Hold Timeson RxOUTPUTsRx power consumption <142 mW (typ) @65MHz
GrayscaleRx Power-down mode <200μW (max) ESD rating>7kV (HBM), >700V (EIAJ) Supports VGA, SVGA, XGA and Dual Pixel SXGA. PLL requiresno external components Compatible with TIA/EIA-644 LVDS standard Low profile 56-leador 48-lead TSSOP package DS90CF384Ais also availableina64 ball, 0.8mm fine
pitch ball grid array (FBGA) package
Block Diagrams
DS90CF384ADS100870-27
Order Number DS90CF384AMTDor DS90CF384ASLC
SeeNS Package Number MTD56or SLC64A
DS90CF364ADS100870-28
Order Number DS90CF364AMTD
SeeNS Package Number MTD48November 2000
DS90CF384A/DS90CF364A
+3.3V
VDS
Receiver
24-Bit-Color
Flat
Panel
Display
(FPD)
Link
MHz
+3.3V
VDS
Receiver
18-Bit-Color
Flat
Panel
Display
(FPD)
Link
MHz
