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DS90C387VJDX-DS90CF388VJD-DS90CF388VJDX
+3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA
DS90C387/DS90CF388
Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA
General DescriptionThe DS90C387/DS90CF388 transmitter/receiver pairis de-
signedto support dual pixel data transmission between Host
and Flat Panel Displayupto QXGA resolutions. The trans-
mitter converts48 bits (Dual Pixel 24-bit color)of CMOS/TTL
data into8 LVDS (Low Voltage Differential Signalling) data
streams. Control signals (VSYNC, HSYNC, DE and two
user-defined signals)are sent during blanking intervals.Ata
maximum dual pixel rate of112MHz, LVDS data line speedis
672Mbps, providinga total throughputof 5.38Gbps (672
Megabytes per second). Two other modes are also sup-
ported. 24-bit color data (single pixel) canbe clocked intothe
transmitterata maximum rateof 170MHz.In this mode,the
transmitter provides single-to-dual pixel conversion, and the
output LVDS clock rateis 85MHz maximum. The third mode
provides inter-operability with FPD-Link devices.
The LDI chipsetis improved over prior generationsof FPD-
Link devices and offers higher bandwidth support and longer
cable drive with three areasof enhancement.To increase
bandwidth,the maximum pixel clock rateis increasedto 112
(170) MHz and8 serialized LVDS outputs are provided.
Cable driveis enhanced witha user selectable pre-
emphasis feature that provides additional output current dur-
ing transitionsto counteract cable loading effects. DC bal-
ancingona cycle-to-cycle basis,is also providedto reduce
ISI (Inter-Symbol Interference). With pre-emphasis and DC
balancing,a low distortion eye-patternis providedat the
receiver endof the cable.A cable deskew capability has
been addedto deskew long cablesof pair-to-pair skewofup +/−1 LVDS databit time(upto80 MHz Clock Rate).These
three enhancements allow cables5+ metersin lengthtobe
driven. This chipsetisan ideal meansto solve EMI and cable
size problemsfor high-resolution flat panel applications.It
providesa reliable interface basedon LVDS technology that
delivers the bandwidth neededfor high-resolution panels
while maximizingbit times, and keeping clock rates lowto
reduce EMI and shielding requirements. For more details,
please refertothe “Applications Information” sectionof this
datasheet.
Features Complies with OpenLDI specificationfor digital display
interfaces 32.5to 112/170MHz clock supportfor DS90C387,40to
112MHz clock supportfor DS90CF388 Supports SVGA through QXGA panel resolutions Drives long, low cost cables Upto 5.38Gbps bandwidth Pre-emphasis reduces cable loading effects DC Balance data transmission providedby transmitter
reducesISI distortion Cable Deskewof +/−1 LVDS databit time (upto80
MHz Clock Rate)of pair-to-pair skewat receiver inputs;
intra-pair skew toleranceof 300ps Dual pixel architecture supports interfaceto GUI and
timing controller; optional single pixel transmitter inputs
support single pixel GUI interface Transmitter rejects cycle-to-cycle jitter5V toleranton data and control input pins Programmable transmitter data and control strobe select
(risingor falling edge strobe) Backward compatible configuration select with FPD-Link Optional second LVDS clockfor backward compatibility FPD-Link Supportfor two additional user-defined control signalsin Balanced mode Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard
May 2004
DS90C387/DS90CF388
Dual
Pixel
VDS
Display
Interface
(LDI)-SVGA/QXGA
