DS90C387RVJD ,85MHz Dual 12-Bit Double Pumped Input LDI Transmitter VGA/UXGAFeaturessignalsinthelowswingoperation.Eachinputdatawidthwillbe1/2ofclockcycle.Withaninputclockat85M ..
DS90C387VJD ,+3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGAElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90C387VJD/NOPB ,+3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA 100-TQFP -10 to 70Maximum RatingsSupply Voltage (V )−0.3V to +4VCCCMOS/TTL Input Voltage−0.3V to +5.5VCMOS/TTL Output ..
DS90C387VJDX ,+3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGAapplications. Itn Compatible with ANSI/TIA/EIA-644-1995 LVDS Standardprovides a reliable interface ..
DS90c401 ,Dual Low Voltage Differential Signaling (LVDS) DriverElectrical CharacteristicsOver supply voltage and operating temperature ranges, unless otherwise sp ..
DS90C401M ,Dual Low Voltage Differential Signaling (LVDS) DriverFeaturesn Ultra low power dissipationThe DS90C401 is a dual driver device optimized for highdata ra ..
DS90C387RVJD
85MHz Dual 12-Bit Double Pumped Input LDI Transmitter VGA/UXGA
DS90C387R
85MHz Dual 12-Bit Double Pumped Input LDI Transmitter VGA/UXGA
General DescriptionThe DS90C387R transmitteris designedto support pixel
data transmission froma Hosttoa Flat Panel Displayupto
UXGAresolution.Itis designedtobe compatible with Graph-
ics Memory Controller Hub( GMCH)by implementing two
data per clock and canbe controlledbya two-wire serial
communication interface. Two input modes are supported:
one portof 12-bit( two data per clock) inputfor 24-bit RGB,
and two portsof 12-bit( two data per clock) inputfor dual
24-bit RGB( 48-bit total).In both modes, input data willbe
clockedon both rising and falling edgesin LVTTL level
operation,or clockedonthe cross overof differential clock
signalsinthelow swing operation. Each input data widthwill1/2of clock cycle. Withan input clockat 85MHz and input
dataat 170Mbps, the maximum transmission rateof each
LVDS lineis 595Mbps,fora aggregate throughput rateof
2.38Gbps/4.76Gbps.It converts 24/48 bits (Single/Dual
Pixel 24-bit color)of data into4/8 LVDS (Low Voltage Differ-
ential Signaling) data streams. DS90C387R canbe pro-
grammed via the two-wire serial communication interface.
The LVDS output pin-outis identicalto DS90C387. Thus,
this transmitter canbe pairedup with DS90CF388, receiverthe 112MHz LDI chipsetor FPD-Link Receiversin non-DC
Balance mode operation which provides GUI/LCD panel/
mother board vendorsa wide choiceof inter-operation with
LVDS based TFT panels.
DS90C387R also comes with features that canbe foundon
DS90C387. Cable driveis enhanced witha user selectable
pre-emphasis feature that provides additional output current
during transitionsto counteract cable loading effects. DC
Balancingona cycle-to-cycle basisis also providedtore-
duce ISI( Inter-Symbol Interference), control signals(
VSYNC, HSYNC, DE) are sent during blanking intervals.
With pre-emphasis and DC Balancing,a low distortion eye-
patternis providedat the receiver endof the cable. These
enhancements allow cables5to 15+ metersin lengthtobe
driven dependingon media characteristic and pixel clock
speed. Pre-emphasisis availablein boththe DC Balanced
and Non-DC Balanced modes.In the Non-DC Balanced
mode backward compatibility with FPD-Link Receiversis
obtained.
This chipisan ideal solutionto solve EMI and cable size
problemsfor high-resolutionflat panel display applications.It
providesa reliable industry standard interface basedon
LVDS technology that delivers the bandwidth neededfor
high-resolution panels while maximizingbit times, and keep-
ing clock rates lowto reduce EMI and shielding require-
ments. For more details, please referto the “Applications
Information” sectionof this datasheet.
Features Complies with Open LDI specificationfor digital display
interfaces25to 85MHz clock support Supports VGA through UXGA panel resolution Upto 4.76Gbps bandwidthin dual 24-bit RGB in-to-dual
pixel out application. Dual 12-bit Double Pumped Input DVO port. Pre-emphasis reduces cable loading effects. Drives long, low cost cables DC Balance data transmission providedby transmitter
reducesISI distortion Transmitter rejects cycle-to-cycle jitter.(+/− 2nsof input
bit period) Support both LVTTL and low voltage level input(capable 1.0to 1.8V) Two-wire serial communication interfaceupto 400 KHz Programmable input clock and control strobe select Backward compatible configuration with 112MHz LDI
and FPD-Link. Optional second LVDS clockfor backward compatibility FPD-Link Receivers Compatible with TIA/EIA-644
December 2003
DS90C387R
85MHz
Dual
12-Bit
Double
Pumped
Input
LDI
ransmitter
VGA/UXGA
