DS90C387 ,Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGAFeaturesn Complies with OpenLDI specification for digital displayThe DS90C387/DS90CF388 transmitter ..
DS90C387AVJD ,Dual Pixel LVDS Display Interface / FPD-Link TransmitterFeaturessecond).n Supports SVGA through QXGA panel resolutionsThe LDI chipset is improved over prio ..
DS90C387AVJD NOPB ,Dual Pixel LVDS Display Interface / FPD-Link Transmitter 100-TQFP -10 to 70Maximum Ratings (Note 1) Package Derating:DS90C387 A 18.2mW/˚C above +25˚CIf Military/Aerospace spe ..
DS90C387AVJD/NOPB ,Dual Pixel LVDS Display Interface / FPD-Link Transmitter 100-TQFP -10 to 70General DescriptionThe DS90C387A/DS90CF388A transmitter/receiver pair is vides a reliable interface ..
DS90C387RVJD ,85MHz Dual 12-Bit Double Pumped Input LDI Transmitter VGA/UXGAFeaturessignalsinthelowswingoperation.Eachinputdatawidthwillbe1/2ofclockcycle.Withaninputclockat85M ..
DS90C387VJD ,+3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGAElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90C387
Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA
DS90C387/DS90CF388
Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA
General DescriptionThe DS90C387/DS90CF388 transmitter/receiver pairis de-
signedto support dual pixel data transmission between Host
and Flat Panel Displayupto QXGA resolutions. The trans-
mitter converts48 bits (Dual Pixel 24-bit color)of CMOS/TTL
data into8 LVDS (Low Voltage Differential Signalling) data
streams. Control signals (VSYNC, HSYNC, DE and two
user-defined signals)are sent during blanking intervals.Ata
maximum dual pixel rate of112MHz, LVDS data line speedis
672Mbps, providinga total throughputof 5.38Gbps (672
Megabytes per second). Two other modes are also sup-
ported. 24-bit color data (single pixel) canbe clocked intothe
transmitterata maximum rateof 170MHz.In this mode, the
transmitter provides single-to-dual pixel conversion, and the
output LVDS clock rateis 85MHz maximum. The third mode
provides inter-operability with FPD-Link devices.
The LDI chipsetis improved over prior generationsof
FPD-Link devices and offers higher bandwidth support and
longer cable drive with three areasof enhancement.To
increase bandwidth, the maximum pixel clock rateisin-
creasedto 112 (170) MHz and8 serialized LVDS outputs are
provided. Cable driveis enhanced witha user selectable
pre-emphasis feature that provides additional output current
during transitionsto counteract cable loading effects. DC
balancingona cycle-to-cycle basis,is also providedtore-
duceISI (Inter-Symbol Interference). With pre-emphasis and balancing,a low distortion eye-patternis providedatthe
receiver endof the cable.A cable deskew capability has
been addedto deskew long cablesof pair-to-pair skewofup +/−1 LVDS databit time(upto80 MHz Clock Rate).These
three enhancements allow cables5to 10+ metersin lengthbe driven. (Continued)
Features Complies with OpenLDI specificationfor digital display
interfaces 32.5to 112/170MHz clock support Supports SVGA through QXGA panel resolutions Drives long, low cost cables Upto 5.38Gbps bandwidth Pre-emphasis reduces cable loading effects DC balance data transmission providedby transmitter
reducesISI distortion Cable Deskewof +/−1 LVDS databit time (upto80
MHz Clock Rate)of pair-to-pair skewat receiver inputs;
intra-pair skew toleranceof 300ps Dual pixel architecture supports interfaceto GUI and
timing controller; optional single pixel transmitter inputs
support single pixel GUI interface Transmitter rejects cycle-to-cycle jitter5V toleranton data and control input pins Programmable transmitter data and control strobe select
(risingor falling edge strobe) Backward compatible configuration select with FPD-Link Optional second LVDS clockfor backward compatibility FPD-Link Supportfor two additional user-defined control signalsin Balanced mode Compatible with TIA/EIA- LVDS Standard
Generalized Block DiagramDS100073-1
PRELIMINARYNovember 2000
DS90C387/DS90CF388
Dual
Pixel
VDS
Display
Interface
(LDI)-SVGA/QXGA
