DS90C385AMTX/NOPB ,LVDS Transmitter Flat Panel Display 85MHz 56-TSSOP -10 to 70features• No Special Start-Up Sequence Requiredand improvements making it an ideal replacement forb ..
DS90C385MTD ,+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-85 MHz/ +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) LFeaturesn 20 to 85 MHz shift clock supportThe DS90C385 transmitter converts 28 bits of CMOS/TTLdata ..
DS90C385MTDX ,+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-85 MHzFeaturesn 20 to 85 MHz shift clock supportThe DS90C385 transmitter converts 28 bits of CMOS/TTLdata ..
DS90C387 ,Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGAFeaturesn Complies with OpenLDI specification for digital displayThe DS90C387/DS90CF388 transmitter ..
DS90C387AVJD ,Dual Pixel LVDS Display Interface / FPD-Link TransmitterFeaturessecond).n Supports SVGA through QXGA panel resolutionsThe LDI chipset is improved over prio ..
DS90C387AVJD NOPB ,Dual Pixel LVDS Display Interface / FPD-Link Transmitter 100-TQFP -10 to 70Maximum Ratings (Note 1) Package Derating:DS90C387 A 18.2mW/˚C above +25˚CIf Military/Aerospace spe ..
DS90C385AMT/ NOPB-DS90C385AMTX/NOPB
LVDS Transmitter Flat Panel Display 85MHz
DS90C385A
www.ti.com SNLS167K –MARCH 2004–REVISED APRIL 2013
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display Link-87.5 MHz
Checkfor Samples: DS90C385A
1FEATURES DESCRIPTIONThe DS90C385A is a pin to pin compatible
23• Pin-to-Pin Compatibleto DS90C383, replacement for DS90C383, DS90C383A and
DS90C383A and DS90C385 DS90C385. The DS90C385A has additional features
• No Special Start-Up Sequence Required and improvements makingit an ideal replacement for
between Clock/Data and /PD Pins. Input DS90C383, DS90C383A and DS90C385. familyof
Signals (Clock and Data) canbe Applied Either LVDS Transmitters.
Beforeor After the Deviceis Powered. The DS90C385A transmitter converts 28 bits of
• Support Spread Spectrum Clocking upto LVCMOS/LVTTL data into four LVDS (Low Voltage
100kHz Frequency Modulation and Deviations Differential Signaling) data streams.A phase-locked
±2.5% Center Spreador -5% Down Spread transmit clockis transmittedin parallel with the data
streams over the fifth LVDS link. Every cycleof the
• “Input Clock Detection" Feature Will Pull All transmit clock 28 bitsof input data are sampled and
LVDS Pairsto Logic Low When Input Clockis transmitted. Ata transmit clock frequencyof 87.5
Missing and When /PD Pinis Logic High MHz, 24 bitsof RGB data and3 bitsof LCD timing
• 18to 87.5 MHz Shift Clock Support and control data (FPLINE, FPFRAME, DRDY) are
Tx Power Consumption< 147 mW (typ)at transmittedata rateof 612.5Mbps per LVDS data
channel. Usinga 87.5 MHz clock, the data throughput
87.5MHz Grayscale 306.25Mbytes/sec. This transmitter can be
• Tx Power-Down Mode<60 μW (typ) programmed for Rising edge strobeor Falling edge
• Supports VGA, SVGA, XGA, SXGA(Dual Pixel), strobe througha dedicated pin.A Rising edge or
SXGA+(Dual Pixel), UXGA(Dual Pixel). Falling edge strobe transmitter will interoperate witha
Falling edge strobe FPDLink Receiver without any
• Narrow Bus Reduces Cable Size and Costtranslation logic.
• Upto 2.45 Gbps ThroughputThis chipsetis an ideal meansto solve EMI and
• Upto 306.25Megabyte/sec Bandwidth cable size problems associated with wide, high-speed
• 345 mV (typ) Swing LVDS Devices for Low EMI TTL interfaces with added Spread Spectrum Clocking
• PLL Requires No External Components support.
Compliantto TIA/EIA-644 LVDS standard Low Profile 56-lead TSSOP Package
Block Diagram
Figure1. DS90C385A
