DS90C383SLC ,+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHzFeaturesn 20 to 65 MHz shift clock supportThe DS90C383 transmitter converts 28 bits of LVCMOS/LVTTL ..
DS90C385AMT ,LVDS Transmitter Flat Panel Display 85MHzfeaturesandimprovementsmakingitanideal n No special start-up sequence required betweenreplacement f ..
DS90C385AMT/ NOPB ,LVDS Transmitter Flat Panel Display 85MHz 56-TSSOP -10 to 70Electrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90C385AMTX ,LVDS Transmitter Flat Panel Display 85MHzElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90C385AMTX/NOPB ,LVDS Transmitter Flat Panel Display 85MHz 56-TSSOP -10 to 70features• No Special Start-Up Sequence Requiredand improvements making it an ideal replacement forb ..
DS90C385MTD ,+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-85 MHz/ +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) LFeaturesn 20 to 85 MHz shift clock supportThe DS90C385 transmitter converts 28 bits of CMOS/TTLdata ..
DS90C383SLC
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
DS90C383/DS90CF384
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel
Display (FPD) Link—65 MHz, +3.3V LVDS Receiver
24-Bit Flat Panel Display (FPD) Link—65 MHz
General DescriptionThe DS90C383 transmitter converts28 bitsof LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signal-
ing) data streams.A phase-locked transmit clockis transmit-
tedin parallel with the data streams overa fifth LVDS link.
Every cycleof the transmit clock28 bitsof input data are
sampled and transmitted. The DS90CF384 receiver con-
vertsthe LVDS data streams back into28 bitsof LVCMOS/
LVTTL data.Ata transmit clock frequencyof65 MHz,24 bits RGB data and3 bitsof LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmittedata rateof 455
Mbps per LVDS data channel. Usinga65 MHz clock, the
data throughputsis 227 Mbytes/sec. The transmitterisof-
fered with programmable edge data strobesfor convenient
interface witha varietyof graphics controllers. The transmit-
ter canbe programmedfor Rising edge strobeor Falling
edge strobe througha dedicated pin.A Rising edge trans-
mitter will inter-operate witha Falling edge receiver
(DS90CF384) without any translation logic. Both devices are
also offeredina64 ball, 0.8mm fine pitch ball grid array
(FBGA) package which providesa44% reductionin PCB
footprint comparedtothe TSSOP package.
This chipsetisan ideal meansto solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features20to65 MHz shift clock support Programmable transmitter (DS90C383) strobe select
(Risingor Falling edge strobe) Single 3.3V supply Chipset (Tx+ Rx) power consumption< 250 mW (typ) Power-down mode(< 0.5 mW total) Single pixelper clock XGA (1024x768) ready Supports VGA, SVGA, XGA and higher addressability. Upto 227 Megabytes/sec bandwidth Upto1.8 Gbps throughput Narrow bus reduces cable size and cost 290 mV swing LVDS devicesfor low EMI PLL requiresno external components Low profile 56-lead TSSOP package. Also availableina64 ball, 0.8mm fine pitch ball grid
array (FBGA) package Falling edge data strobe Receiver Compatible with TIA/EIA-644 LVDS standard ESD rating >7kV Operating Temperature: −40˚Cto +85˚C
Block Diagrams
Typical ApplicationDS012887-2
November 2000
DS90C383/DS90CF384
+3.3V
Programmable
VDS
24-Bit-Color
Flat
Panel
Display
(FPD)
Link
MHz
