DS90C363BMTX ,+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) LinkElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90C363BMTX ,+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) LinkBlock DiagramDS90C363B20098601Order Number DS90C363BMTSee NS Package Number MTD48®TRI-STATE is a re ..
DS90C363MTD ,+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHzFeaturesn 20 to 65 MHz shift clock supportThe DS90C363 transmitter converts 21 bits of CMOS/TTLdata ..
DS90C363MTDX ,+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHzBlock DiagramsApplicationDS012886-14®TRI-STATE is a registered trademark of National Semiconductor ..
DS90C365AMT ,LVDS Transmitter Flat Panel Display 85MHzfeaturesandimprovementsmakingitanidealn Support Spread Spectrum Clocking up to 100kHzreplacement fo ..
DS90C365AMT ,LVDS Transmitter Flat Panel Display 85MHzBlock DiagramDS90C365A20100539Order Number DS90C365AMTSee NS Package Number MTD48 2004 National Sem ..
DS90C363BMT-DS90C363BMTX
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link
DS90C363B
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel
Display (FPD) Link -65 MHz
General DescriptionThe DS90C363B transmitter converts21 bitsof CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. Aphase-locked transmit clockis transmittedin
parallel withthe data streams overa fourth LVDS link. Every
cycleofthe transmit clock21 bitsof input dataare sampled
and transmitted.Ata transmit clock frequencyof65 MHz,18
bitsof RGB data and3 bitsof LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmittedata rateof 455
Mbps per LVDS data channel. Usinga65 MHz clock, the
data throughputis 170 Mbytes/sec. The DS90C363B trans-
mitter canbe programmedfor Rising edge strobeor Falling
edge strobe througha dedicated pin.A Rising edgeor
Falling edge strobe transmitterwill interoperate witha Falling
edge strobe Receiver (DS90CF366) without any translation
logic.
This chipsetisan ideal meansto solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features No special start-up sequence required between
clock/data and /PD pins. Input signal (clock and data)
canbe applied either beforeor afterthe deviceis
powered. Support Spread Spectrum Clockingupto 100kHz
frequency modulation& deviationsof ±2.5% center
spreador −5% down spread. "Input Clock Detection" featurewill pullall LVDS pairsto
logic low when input clockis missing and when /PDpin logic high.18to68 MHz shift clock support Best–in–Class Set& Hold Timeson TxINPUTsTx power consumption< 130 mW (typ) @65MHz
Grayscale 40% Less Power Dissipation than BiCMOS AlternativesTx Power-down mode< 37µW (typ) Supports VGA, SVGA, XGA and Dual Pixel SXGA. Narrow bus reduces cable size and cost Upto1.3 Gbps throughput Upto 170 Megabytes/sec bandwidth 345 mV (typ) swing LVDS devicesfor low EMI PLL requiresno external components Compatible with TIA/EIA-644 LVDS standard Low profile 48-lead TSSOP package Improved replacement for:
SN75LVDS84, DS90C363A
Block Diagram
DS90C363BOrder Number DS90C363BMT
See NS Package Number MTD48
PRELIMINARY
July 2004
+3.3V
Programmable
VDS
ransmitter
18-Bit
Flat
Panel
Display
(FPD)
Link
MHz
