DS90C3201VS ,3.3V 8 MHz to 135 MHz Dual FPD-Link TransmitterFunctional Descriptionmode,bothDOX[A-E]andDOY[A-E]LVDSportsforoddandThe DS90C3201 and DS90C3202 are ..
DS90C363AMTD ,+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) LinkFeaturesn 20 to 65 MHz shift clock supportThe DS90C363A/DS90CF363A transmitter converts 21 bitsofCM ..
DS90C363AMTDX ,+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) LinkElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90C363BMT ,+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) LinkFeaturesn No special start-up sequence required betweenThe DS90C363B transmitter converts 21 bits o ..
DS90C363BMTX ,+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) LinkElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90C363BMTX ,+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) LinkBlock DiagramDS90C363B20098601Order Number DS90C363BMTSee NS Package Number MTD48®TRI-STATE is a re ..
DS90C3201VS
3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter
DS90C3201
3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter
General DescriptionThe DS90C3201isa 3.3V single/dual FPD-Link 10-bit color
transmitteris designedtobe usedin Liquid Crystal Display
TVs, LCD Monitors, Digital TVs, and Plasma Display Panel
TVs. The DS90C3201is designedto interface between the
digital video processor and the display device using the
low-power, low-EMI LVDS (Low Voltage Differential Signal-
ing) interface. The DS90C3201 convertsupto70 bitsof
LVCMOS/LVTTL data into ten LVDS data streams. The
transmitter canbe programmed clocking data with rising
edgeor falling edge clock. Optional two-wire serial program-
ming allows fine tuningin development and production en-
vironments.Ata transmitted clock frequencyof 135 MHz,70
bitsof LVCMOS/LVTTL data are transmittedatan effective
rateof 945 Mbpsper LVDS channel. Usinga 135 MHz clock,
the data throughputis 9.45Gbit/s (945Mbytes/s). This allows
the dual 10-bit LVDS Transmitterto support HDTV resolu-
tions.
Features Upto 9.45Gbit/s data throughput8 MHzto 135 MHz input clock support Supportsupto QXGA panel resolutions Supports HDTV resolutions and frame ratesupto
1920x 1080p LVDS 30-bit, 24-bitor 18-bit color data outputs Supports single pixel and dual pixel interfaces Supports spread spectrum clocking Two-wire serial communication interface Programmable clock edge and control strobe select Power down mode +3.3V supply voltage 128-pin TQFP Compliantto TIA/EIA-644-A-2001 LVDS Standard Backward compatible configuration with FPD-Link
Block DiagramFIGURE1. Transmitter Block Diagram
ADVANCE INFORMATION
April 2005
DS90C3201
3.3V
MHz
MHz
Dual
FPD-Link
ransmitter
