DS90C032W-QMLV ,LVDS Quad CMOS Differential Line Receiver 16-CFP -55 to 125FEATURES DESCRIPTIONThe DS90C032 is a quad CMOS differential line2• Single Event Latchup (SEL) Immu ..
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DS90C032W-QMLV
LVDS Quad CMOS Differential Line Receiver
DS90C032QML
www.ti.com SNLS203D –MARCH 2006–REVISED APRIL 2013
DS90C032QML LVDS Quad CMOS Differential Line Receiver
Checkfor Samples: DS90C032QML
1FEATURES DESCRIPTIONThe DS90C032isa quad CMOS differential line
Single Event Latchup (SEL) Immune 120 MeV- receiver designed for applications requiring ultra low
cm2 /mg power dissipation and high data rates.
• High Impedance LVDS Inputs with Power-Off. The DS90C032 accepts low voltage differential input
• Accepts Small Swing (330 mV) Differential signals and translates them to CMOS (TTL
Signal Levels compatible) output levels. The receiver supportsa
• Low Power Dissipation TRI-STATE function that may be usedto multiplex
outputs. The receiver also supports OPEN Failsafe
• Low Differential Skew and terminated (100Ω) input Failsafe with the addition
• Low Chipto Chip Skew of external failsafe biasing. Receiver output will be
• Pin Compatible with DS26C32A HIGHfor both Failsafe conditions.
Compatible with IEEE 1596.3 SCI LVDS The DS90C032 provides power-off high impedance
Standard LVDS inputs. This feature assures minimal loading
effect on the LVDS bus lines when VCCis not
present.
The DS90C032 and companion line driver
(DS90C031) providea new alternativeto high power
pseudo-ECL devices for high speed point-to-point
interface applications.
Connection Diagrams Figure& NAC0016A See Package
