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DS90C032TMX/NOPB |DS90C032TMXNOPBNSCN/a2010avaiLVDS Quad CMOS Differential Line Receiver 16-SOIC -40 to 85


DS90C032TMX/NOPB ,LVDS Quad CMOS Differential Line Receiver 16-SOIC -40 to 85Maximum RatingsSupply Voltage (V )−0.3V to +6VCCInput Voltage (R , R )−0.3V to (V +0.3V)IN+ IN− CCE ..
DS90C032W-QMLV ,LVDS Quad CMOS Differential Line Receiver 16-CFP -55 to 125FEATURES DESCRIPTIONThe DS90C032 is a quad CMOS differential line2• Single Event Latchup (SEL) Immu ..
DS90C124IVS , 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS90C124IVSX , 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS90C124IVSX/NOPB ,5-35MHz DC- Balanced 24-Bit FPD-Link II Deserializer 48-TQFP -40 to 105 SNLS209M–NOVEMBER 2005–REVISED JANUARY 20175 Pin Configuration and FunctionsDS90C241 Serializer PF ..
DS90C124QVS/NOPB ,5-35MHz DC- Balanced 24-Bit FPD-Link II Deserializer 48-TQFP -40 to 105 SNLS209M–NOVEMBER 2005–REVISED JANUARY 20175 Pin Configuration and FunctionsDS90C241 Serializer PF ..


DS90C032TMX/NOPB
LVDS Quad CMOS Differential Line Receiver
DS90C032
www.ti.com
SNLS094D–JUNE 1998–REVISED APRIL 2013
DS90C032 LVDS Quad CMOS Differential Line Receiver
Checkfor Samples: DS90C032
1FEATURES DESCRIPTION

TheDS90C032 isa quad CMOS differential line >155.5 Mbps (77.7 MHz) switching rates receiver designed for applications requiring ultra low• Accepts small swing (350 mV) differential power dissipation and high data rates. The devicesignal levels supports data ratesin excessof 155.5 Mbps (77.7 Ultra low power dissipation MHz) and uses Low Voltage Differential Signaling
(LVDS) technology.• 600 ps maximum differential skew (5V, 25°C)
TheDS90C032 accepts low voltage (350 mV)• 6.0 ns maximum propagation delay
differential input signals and translates them to• Industrial operating temperature range CMOS (TTL compatible) output levels. The receiver• Military operating temperature range option supportsa TRI-STATE function that may be usedto Availablein surface mount packaging (SOIC) multiplex outputs. The receiver also supports OPEN,
shorted, and terminated (100Ω) input Failsafe withand (LCCC)
the addition of external failsafe biasing. Receiver• Pin compatible with DS26C32A, MB570 output willbe HIGH for both Failsafe conditions.(PECL), and 41LF (PECL)
TheDS90C032 and companion line driver• Supports OPEN input fail-safe (DS90C031) providea new alternativeto high power• Supports short and terminated input fail-safe pseudo-ECL devices for high speed point-to-pointwith the additionof external failsafe biasing interface applications. Compatible with IEEE 1596.3 SCI LVDS
standard Conformsto ANSI/TIA/EIA-644 LVDS standard Availableto Standard Microcircuit Drawing
(SMD) 5962-95834
Connection Diagram
Dual-In-Line1. See Package NumberD (R-PDSO-G16)
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