DS90C032BTM ,LVDS Quad CMOS Differential Line ReceiverFeatures>n 155.5 Mbps (77.7 MHz) switching ratesTheDS90C032B is a quad CMOS differential line recei ..
DS90C032BTM/NOPB ,LVDS Quad CMOS Differential Line Receiver 16-SOIC -40 to 85Maximum RatingsSupply Voltage (V )−0.3V to +6VCCInput Voltage (R , R )−0.3V to +5.8VIN+ IN−Enable I ..
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DS90C032BTM
LVDS Quad CMOS Differential Line Receiver
DS90C032B
LVDS Quad CMOS Differential Line Receiver
General DescriptionTheDS90C032Bisa quad CMOS differential line receiver
designedfor applications requiring ultra low power dissipa-
tion and high data rates. The deviceis designedto support
data ratesin excessof 155.5 Mbps (77.7 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.
TheDS90C032B accepts low voltage (350 mV) differential
input signals and translates themto CMOS (TTLcompatible)
output levels. The receiver supportsa TRI-STATE® function
that maybe usedto multiplex outputs. The receiver also
supports OPEN Failsafe and terminated (100Ω) input Fail-
safe with the additionof external failsafe biasing. Receiver
output willbe HIGHfor both Failsafe conditions.
The DS90C032Bprovides power-off high impedance LVDS
inputs. This feature assures minimal loading effecton the
LVDS bus lines when VCCisnot present.
The DS90C032Band companion line driver (DS90C031B)
providea new alternativeto high power pseudo-ECLdevices
for high speed point-to-point interface applications.
Features >155.5 Mbps (77.7 MHz) switching rates Accepts small swing (350 mV) differential signal levels High Impedance LVDS inputs with power down Ultra low power dissipation 600ps maximum differential skew (5V, 25˚C) 6.0ns maximum propagation delay Industrial operating temperature range Availablein surface mount packaging (SOIC) Pin compatible with DS26C32A, MB570 (PECL) and
41LF (PECL) Supports OPEN and terminated input failsafe Conformsto ANSI/TIA/EIA-644 LVDS standard
Connection Diagram
Dual-In-LineOrder Number
DS90C032BTM
See NS Package
Number M16A
Functional Diagram
Receiver Truth Table
ENABLES INPUTS OUTPUT EN* RIN+ −RIN− ROUT X Z
All other
combinations ENABLE
inputs
VID≥ 0.1V H
VID≤ −0.1V L
Failsafe OPEN H Terminated
September 2003
DS90C032BL
VDS
Quad
CMOS
Differential
Line
Receiver
