DS90C032BTMX ,LVDS Quad CMOS Differential Line ReceiverFEATURES DESCRIPTIONThe DS90C032B is a quad CMOS differential line2• >155.5 Mbps (77.7 MHz) Switchi ..
DS90C032E-QML ,LVDS Quad CMOS Differential Line Receiverapplications.n Available to Standard Microcircuit Drawing (SMD)5962-95834Connection DiagramsDual-In ..
DS90C032TM ,LVDS Quad CMOS Differential Line ReceiverMICROCIRCUIT DATA SHEETOriginal Creation Date: 04/14/00MNDS90C032-X-RH REV 1B1Last Update Date: 08/ ..
DS90C032TMX ,LVDS Quad CMOS Differential Line ReceiverFeatures- High impedance LVDS inputs with power-off - Accepts small swing (330 mV) differential sig ..
DS90C032TMX/NOPB ,LVDS Quad CMOS Differential Line Receiver 16-SOIC -40 to 85Maximum RatingsSupply Voltage (V )−0.3V to +6VCCInput Voltage (R , R )−0.3V to (V +0.3V)IN+ IN− CCE ..
DS90C032W-QMLV ,LVDS Quad CMOS Differential Line Receiver 16-CFP -55 to 125FEATURES DESCRIPTIONThe DS90C032 is a quad CMOS differential line2• Single Event Latchup (SEL) Immu ..
DS90C032BTM/NOPB-DS90C032BTMX
LVDS Quad CMOS Differential Line Receiver
DS90C032B
www.ti.com SNLS052C –MARCH 1999–REVISED APRIL 2013
DS90C032B LVDS Quad CMOS Differential Line Receiver
Checkfor Samples: DS90C032B
1FEATURES DESCRIPTIONThe DS90C032Bisa quad CMOS differential line
>155.5 Mbps (77.7 MHz) Switching Rates receiver designed for applications requiring ultra low
• Accepts Small Swing (350 mV) Differential power dissipation and high data rates. The device
Signal Levels supports data rates in excess of 155.5 Mbps
High Impedance LVDS Inputs with Power (77.7 MHz) and uses Low Voltage Differential
Signaling (LVDS) technology.
Down Ultra Low Power Dissipation The DS90C032B accepts low voltage (350 mV)
differential input signals and translates them to
• 600 ps Maximum Differential Skew (5V, 25°C) CMOS (TTL compatible) output levels. The receiver
• 6.0 ns Maximum Propagation Delay supportsa TRI-STATE function that may be usedto
• Industrial Operating Temperature Range multiplex outputs. The receiver also supports OPEN
Failsafe and terminated (100Ω) input Failsafe with the
• Availablein Surface Mount Packaging (SOIC)additionof external failsafe biasing. Receiver output
• Pin Compatible with DS26C32A, MB570 (PECL) will be HIGHfor both Failsafe conditions.
and 41LF (PECL)The DS90C032B provides power-off high impedance
• Supports OPEN and Terminated Input Failsafe LVDS inputs. This feature assures minimal loading
• Conformsto ANSI/TIA/EIA-644 LVDS Standard effect on the LVDS bus lines when VCCis not
present.
The DS90C032B and companion line driver
(DS90C031B) providea new alternative to high
power pseudo-ECL devices for high-speed point-to-
point interface applications.
Connection Diagram Functional Diagram (R-PDSO-G16)
