DS89C430-ENL ,Ultra-High-Speed Flash MicrocontrollersELECTRICAL CHARACTERISTICS (V = 4.5V to 5.5V, T = -40°C to +85°C.) (Note 1) CC O PARAMETER SYMBOL M ..
DS89C430-ENL+ ,Ultra-High-Speed Flash MicrocontrollersDS89C430/DS89C450Ultra-High-Speed Flash Microcontrollers
DS89C430MNG ,Ultra-High-Speed Flash MicrocontrollersELECTRICAL CHARACTERISTICS (V = 4.5V to 5.5V, T = -40°C to +85°C.) (Note 1) CC O PARAMETER SYMBOL M ..
DS89C430-MNG ,Ultra-High-Speed Flash MicrocontrollersELECTRICAL CHARACTERISTICS (V = 4.5V to 5.5V, T = -40°C to +85°C.) (Note 1) CC O PARAMETER SYMBOL M ..
DS89C430-MNG+ ,Ultra-High-Speed Flash MicrocontrollersELECTRICAL CHARACTERISTICS (V = 4.5V to 5.5V, T = -40°C to +85°C.) (Note 1) CC O PARAMETER SYMBOL M ..
DS89C430MNL ,Ultra-High-Speed Flash Microcontrollersapplications will experience a Fast/Slow Peripherals speed improvement up to 10x. At 1 million Dual ..
DS89C430ENL-DS89C430-ENL-DS89C430MNL-DS89C430-MNL-DS89C430-QNL-DS89C440ENL-DS89C450ENL-DS89C450MNL-DS89C450-MNL-DS89C450-QNL
Ultra-High-Speed Flash Microcontrollers
GENERAL DESCRIPTION The DS89C430, DS89C440, and DS89C450 offer the highest performance available in 8051-compatible
microcontrollers. They feature newly designed
processor cores that execute instructions up to 12 times faster than the original 8051 at the same
crystal speed. Typical applications will experience a speed improvement up to 10x. At 1 million instructions per second (MIPS) per megahertz, the
microcontrollers achieve 33 MIPS performance from
a maximum 33MHz clock rate.
The Ultra-High-Speed Flash Microcontroller User’s Guide should
be used in conjunction with this data sheet. Download it at
/microcontrollers. APPLICATIONS Data Logging Vending
Automotive Test Equipment Motor Control
Magstripe Reader/Scanner Consumer Electronics
Gaming Equipment Telephones
HVAC Programmable Logic
Controllers Uninterruptible Power Supplies Building Security and Door Access Control Building Energy Control and
Management Industrial Control and Automation White Goods (Washers, Microwaves, etc.)
ORDERING INFORMATION
Complete Selector Guide appears at end of data sheet.
Pin Configurations appear at end of data sheet.
FEATURES High-Speed 8051 Architecture One Clock-Per-Machine Cycle DC to 33MHz Operation
Single Cycle Instruction in 30ns Optional Variable Length MOVX to Access
Fast/Slow Peripherals Dual Data Pointers with Automatic Increment/Decrement and Toggle Select
Supports Four Paged Memory-Access Modes
On-Chip Memory 16kB/32kB/64kB Flash Memory In-Application Programmable
In-System Programmable Through Serial Port
1kB SRAM for MOVX
80C52 Compatible 8051 Pin and Instruction Set Compatible
Four Bidirectional, 8-Bit I/O Ports
Three 16-Bit Timer Counters 256 Bytes Scratchpad RAM
Power-Management Mode Programmable Clock Divider
Automatic Hardware and Software Exit
ROMSIZE Feature Selects Internal Program Memory Size from
0 to 64kB
Allows Access to Entire External Memory Map Dynamically Adjustable by Software
Peripheral Features Two Full-Duplex Serial Ports
Programmable Watchdog Timer 13 Interrupt Sources (Six External) Five Levels of Interrupt Priority
Power-Fail Reset Early Warning Power-Fail Interrupt
Electromagnetic Interference (EMI) Reduction
DS89C430/DS89C440/DS89C450
Ultra-High-Speed Flash Microcontrollers
DS89C430/DS89C44/DS89C450 Ultra-High-Speed Flash Microcontrollers
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground
-0.3V to (VCC + 0.5V)
Voltage Range on VCC Relative to Ground
..-0.3V to +6.0V Ambient Temperature Range (under bias)
-40°C to +85°C Storage Temperature Range
.-55°C to +125°C
Soldering Temperature
See IPC/JEDEC J-STD-020A
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (Note 1)
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: All voltages are referenced to ground.
Note 3: The user should note that this part is tested and guaranteed to operate down to 4.5V (10%) and that VRST (min) is specified below
that point. This indicates that there is a range of voltages [(VMIN to VRST (min)] where the processor's operation is not guaranteed, but
the reset trip point has not been reached. This should not be an issue in most applications, but should be considered when proper
operation must be maintained at all times. For these applications, it may be desirable to use a more accurate external reset.
Note 4: While the specifications for VPFW and VRST overlap, the design of the hardware makes it so this is not possible. Within the ranges
given, there is guaranteed separation between these two voltages.
Note 5: Active current is measured with a 33MHz clock source driving XTAL1, VCC = RST = 5.5V. All other pins are disconnected.
Note 6: Idle mode current is measured with a 33MHz clock source driving XTAL1, VCC = 5.5V, RST at ground. All other pins are
disconnected.
Note 7: Stop mode is measured with XTAL and RST grounded, VCC = 5.5V. All other pins are disconnected.
Note 8: RST = 5.5V. This condition mimics the operation of pins in I/O mode.
Note 9: During a 0-to-1 transition, a one shot drives the ports hard for two clock cycles. This measurement reflects a port pin in transition
mode.
Note 10: When addressing external memory.
Note 11: Guaranteed by design.
Note 12: Ports 1, 2, and 3 source transition current when pulled down externally. The current reaches its maximum at approximately 2V.
Note 13: RST = 5.5V. Port 0 is floating during reset and when in the logic-high state during I/O mode.
Note 14: This port is a weak address holding latch in bus mode. Peak current occurs near the input transition point of the holding latch at
approximately 2V.
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DS89C430/DS89C440/DS89C450
Note 15: The clock divide and crystal multiplier control bits in the PMR register determine the system clock frequency and the minimum/
maximum external clock speed. The term 1/tCLCL used in the AC Characteristics variable timing table is determined from the
following table. The minimum/maximum external clock speed columns clarify that [(external clock speed) x (multipliers)] cannot
exceed the rated speed of the device. In addition, the use of the crystal multiplier feature establishes a minimum external speed.
Note 16: External MOVX instruction times are dependent upon the setting of the MD2, MD1, and MD0 bits in the clock control register. The
terms tSTC1, tSTC2, tSTC3 used in the variable timing table above are calculated through the use of the table given below.
Note 17: Maximum load capacitance (to meet the above timing) for Port 0, ALE, PSEN, WR, and RD is limited to 60pF. XTAL1 and XTAL2 load
capacitance are dependent upon the frequency of the selected crystal.
Figure 1. Nonpage Mode Timing
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Figure 2. Page Mode 1 Timing
Figure 3. Page Mode 2 Timing
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
EXTERNAL CLOCK CHARACTERISTICS
(VCC = 4.5V to 5.5V, TO = -40°C to +85°C.)
SERIAL PORT MODE 0 TIMING CHARACTERISTICS
(VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (Figure 4)
Note: SM2 is the serial port 0 mode bit 2. When serial port 0 is operating in mode 0 (SM0 = SM1 = 0), SM2 determines the number of crystal
clocks in a serial port clock cycle.
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Figure 4. Serial Port Timing
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
POWER-CYCLE TIMING CHARACTERISTICS
(VCC = 4.5V to 5.5V, TO = -40°C to +85°C.)
Note 18: Startup time for a crystal varies with load capacitance and manufacturer. The time shown is for an 11.0592MHz crystal manufactured
by Fox Electronics.
Note 19: Reset delay is a synchronous counter of crystal oscillations after crystal startup. Counting begins when the level on the XTAL1 pin
meets the VIH2 criteria. At 33MHz, this time is 1.99ms.
FLASH MEMORY PROGRAMMING CHARACTERISTICS
(VCC = 4.5V to 5.5V)
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
PIN DESCRIPTION
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
PIN DESCRIPTION (continued)
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Figure 5. Functional Diagram DETAILED DESCRIPTION
The DS89C430, DS89C440, and DS89C450 are pin compatible with all three packages of the standard 8051 and
include standard resources such as three timer/counters, serial port, and four 8-bit I/O ports. The three part numbers vary only by the amount of internal flash memory (DS89C430 = 16kB, DS89C440 = 32kB, DS89C450 =
64kB), which can be in-system/in-application programmed from a serial port using ROM-resident or user-defined loader software. For volume deployments, the flash can also be loaded externally using standard commercially
available parallel programmers.
Besides greater speed, the DS89C430/DS89C440/DS89C450 include 1kB of data RAM, a second full hardware
serial port, seven additional interrupts, two extra levels of interrupt priority, programmable watchdog timer, brownout monitor, and power-fail reset. Dual data pointers (DPTRs) are included to speed up block data-memory
moves with further enhancements coming from selectable automatic increment/decrement and toggle select operation. The speed of MOVX data memory access can be adjusted by adding stretch values up to 10 machine
cycles for flexibility in selecting external memory and peripherals.
A power management mode consumes significantly lower power by slowing the CPU execution rate from one clock
period per cycle to 1024 clock periods per cycle. A selectable switchback feature can automatically cancel this mode to enable normal speed responses to interrupts.
For EMI-sensitive applications, the microcontroller can disable the ALE signal when the processor is not accessing
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Terminology
The term DS89C430 is used in the remainder of the document to refer to the DS89C430, DS89C440, and
DS89C450, unless otherwise specified. Compatibility
The DS89C430 is a fully static CMOS 8051-compatible microcontroller similar in functional features to the
DS87C520, but it offers much higher performance. In most cases, the DS89C430 can drop into an existing socket for the 8xC51 family, immediately improving the operation. While remaining familiar to 8051 family users, the
DS89C430 has many new features. In general, software written for existing 8051-based systems works without modification on the DS89C430, with the exception of critical timing routines, as the DS89C430 performs its
instructions much faster for any given crystal selection.
The DS89C430 provides three 16-bit timer/counters, two full-duplex serial ports, and 256 bytes of direct RAM plus
1kB of extra MOVX RAM. I/O ports can operate as in standard 8051 products. Timers default to 12 clocks-per-cycle operation to keep their timing compatible with a legacy 8051 family systems. However, timers are individually
programmable to run at the new one clock per cycle if desired. The DS89C430 provides several new hardware features, described in subsequent sections, implemented by new special-function registers (SFRs). Performance Overview
Featuring a completely redesigned high-speed 8051-compatible core, the DS89C430 allows operation at a higher
clock frequency. This updated core does not have the wasted memory cycles that are present in a standard 8051. A conventional 8051 generates machine cycles using the clock frequency divided by 12. The same machine cycle
takes one clock in the DS89C430. Thus, the fastest instructions execute 12 times faster for the same crystal frequency (and actually 24 times faster for the INC data pointer instruction). It should be noted that this speed
improvement is reduced when using external memory access modes that require more than one clock per cycle.
Individual program improvement depends on the instructions used. Speed-sensitive applications would make the
most use of instructions that are 12 times faster. However, the sheer number of 12-to-1 improved op codes makes dramatic speed improvements likely for any code. These architectural improvements produce instruction cycle
times as low as 30ns. The dual data pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory. The new page modes allow for increased efficiency in external memory accesses. Instruction Set Summary
All instructions have the same functionality as their 8051 counterparts, including their affect on bits, flags, and other status functions. However, the timing of each instruction is different, in both absolute and relative number of clocks.
For absolute timing of real-time events, the duration of software loops can be calculated using information given in the Instruction Set table in the Ultra-High-Speed Flash Microcontroller Users Guide. However, counter/timers
default to run at the older 12 clocks per increment. In this way, timer-based events occur at the standard intervals with software executing at higher speed. Timers optionally can run at a reduced number of clocks per increment to
take advantage of faster processor operation.
The relative time of some instructions may be different in the new architecture. For example, in the original
architecture, the MOVX A, @DPTR instruction and the MOV direct, direct instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of time. In the DS89C430, the MOVX instruction
takes as little as two machine cycles or two oscillator cycles, but the MOV direct, direct uses three machine cycles or three oscillator cycles. While both are faster than their original counterparts, they now have different execution
times. This is because the DS89C430 usually uses one machine cycle for each instruction byte and requires one cycle for execution. The user concerned with precise program timing should examine the timing of each instruction
to become familiar with the changes.
Special-Function Registers (SFRs)
All peripherals and operations that are not explicit instructions in the DS89C430 are controlled through SFRs. The most common features basic to the architecture are mapped to the SFRs. These include the CPU registers (ACC,
B, and PSW), data pointers, stack pointer, I/O ports, timer/counters, and serial ports. In many cases, an SFR
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
All standard SFR locations from the 8051 are duplicated in the DS89C430, and several SFRs have been added for
the unique features of the DS89C430. Most of these features are controlled by bits in SFRs located in unused locations in the 8051 SFR map, allowing for increased functionality while maintaining complete instruction set
compatibility. Table 1 shows the SFRs and their locations. Table 2 specifies the default reset condition for all SFR bits. Data Pointers
The data pointers (DPTR and DPTR1) are used to assign a memory address for the MOVX instructions. This
address can point to a MOVX RAM location (on-chip or off-chip) or a memory-mapped peripheral. Two pointers are useful when moving data from one memory area to another, or when using a memory-mapped peripheral for both
source and destination addresses. The user can select the active pointer through a dedicated SFR bit (SEL = DPS.0), or can activate an automatic toggling feature for altering the pointer selection (TSL = DPS.5). An additional feature, if selected, provides automatic incrementing or decrementing of the current DPTR. Stack Pointer
The stack pointer denotes the register location at the top of the stack, which is the last used value. The user can
place the stack anywhere in the scratchpad RAM by setting the stack pointer to the desired location, although the lower bytes are normally used for working registers. I/O Ports
The DS89C430 offers four 8-bit I/O ports. Each I/O port is represented by an SFR location and can be written or
read. The I/O port has a latch that contains the value written by software. Counter/Timers
Three 16-bit timer/counters are available in the DS89C430. Each timer is contained in two SFR locations that can
be read or written by software. The timers are controlled by other SFRs, described in the SFR Bit Description section of the Ultra-High-Speed Flash Microcontroller Users Guide. Serial Ports
The DS89C430 provides two UARTs that are controlled and accessed by SFRs. Each UART has an address that
is used to read and write the value contained in the UART. The same address is used for both read and write operations, and the read and write operations are distinguished by the instruction. Its own SFR control register
controls each UART.
Table 1. SFR Register Map
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Table 1. SFR Register Map (continued)
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Table 2. SFR Reset Value
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Table 2. SFR Reset Value (continued)
Note: Consult the Ultra-High-Speed Flash Microcontroller Users Guide for more information about the bits marked Special. Memory Organization
There are three distinct memory areas in the DS89C430: scratchpad registers, program memory, and data
memory. The registers are located on-chip but the program and data memory spaces can be on-chip, off-chip, or both. The DS89C430/DS89C440/DS89C450 have 16kB/32kB/64kB of on-chip program memory, respectively,
implemented in flash memory and also have 1kB of on-chip data memory space that can be configured as program space using the PRAME bit in the ROMSIZE feature. The DS89C430 uses a memory-addressing scheme that
separates program memory from data memory. The program and data segments can be overlapped since they are accessed in different manners. If the maximum address of on-chip program or data memory is exceeded, the
DS89C430 performs an external memory access using the expanded memory bus. The PSEN signal goes active
low to serve as a chip enable or output enable when performing a code fetch from external program memory.
MOVX instructions activate the RD or WR signal for external MOVX data memory access. The program memory ROMSIZE feature allows software to dynamically configure the maximum address of on-chip program memory.
This allows the DS89C430 to act as a bootloader for an external memory. It also enables the use of the overlapping external program spaces. The lower 128 bytes of on-chip flash memoryif ROMSIZE is greater than
0are used to store reset and interrupt vectors. 256 bytes of on-chip RAM serve as a register area and program stack, which are separated from the data memory. Register Space
Registers are located in the 256 bytes of on-chip RAM labeled internal registers (Figure 6), which can be divided
into two sub areas of 128 bytes each. Separate classes of instructions are used to access the registers and the program/data memory. The upper 128 bytes are overlapped with the 128 bytes of SFRs in the memory map. Indirect addressing is used to access the upper 128 bytes of scratchpad RAM, while the SFR area is accessed
using direct addressing. The lower 128 bytes can be accessed using direct or indirect addressing.
There are four banks of eight working registers in the lower 128 bytes of scratchpad RAM. The working registers are general-purpose RAM locations that can be addressed within the selected bank by any instructions that use R0R7. The register bank selection is controlled through the program status register in the SFR area. The contents
of the working registers can be used for indirect addressing of the upper 128 bytes of scratchpad RAM.
Individually addressable bits in the RAM and SFR areas support Boolean operations. In the scratchpad RAM area, registers 20h2Fh are bit addressable by software using Boolean operation instructions.
Another use of the scratchpad RAM area is for the stack. The stack pointer, contained in the SFRs, is used to select storage locations for program variables and for return addresses of control operations.
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Figure 6. Memory Map (as shown for the DS89C430)
Memory Configuration
As illustrated in Figure 6, the DS89C430 incorporates two 8kB flash areas for on-chip program memory and 1kB of SRAM for on-chip data memory or a particular range (4007FF) of alternate program memory space. The
DS89C440 incorporates two 16kB flash memories and the DS89C450 incorporates two 32kB flash memories. The DS89C430 uses an address scheme that separates program memory from data memory such that the 16-bit
address bus can address each memory area up to maximum of 64kB.
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Program Memory Access
On-chip program memory begins at address 0000h and is contiguous through 3FFFh (16kB) on the DS89C430,
through 7FFFh (32kB) on the DS89C440, and through FFFFh (64kB) on the DS89C450. Exceeding the maximum address of on-chip program memory causes the device to access off-chip memory. The maximum on-chip decoded
address is selectable by software using the ROMSIZE feature. Software can cause the DS89C430 to behave like a device with less on-chip memory. This is beneficial when overlapping external memory is used. The maximum memory size is dynamically variable. Thus a portion of memory can be removed from the memory map to access
off-chip memory and then be restored to access on-chip memory. In fact, all the on-chip memory can be removed
from the memory map allowing the full 64kB memory space to be addressed from off-chip memory. Program memory addresses that are larger than the selected maximum are automatically fetched from outside the part
through ports 0 and 2. Figure 6 shows a depiction of the memory map.
The ROMSIZE register is used to select the maximum on-chip decoded address for program memory. Bits RMS2,
RMS1, and RMS0 have the following effect:
The reset default condition for all devices is to their maximum on-chip program memory size. When accessing
external program memory, that amount of external memory would be inaccessible. To select a smaller effective program memory size, software must alter bits RMS2RMS0. Altering these bits requires a timed-access
procedure, as explained later.
Care should be taken so that changing the ROMSIZE register does not corrupt program execution. For example,
assume that a DS89C430 is executing instructions from internal program memory near the 12kB boundary (~3000h) and that the ROMSIZE register is currently configured for a 16kB internal program space. If software
reconfigures the ROMSIZE register to 4kB (0000h0FFFh) in the current state, the device immediately jumps to external program execution because program code from 4kB to 16kB (1000h3FFFh) is no longer located on-chip.
This could result in code misalignment and execution of an invalid instruction. The recommended method is to modify the ROMSIZE register from a location in memory that is internal (or external) both before and after the
operation. In the above example, the instruction that modifies the ROMSIZE register should be located below the 4kB (1000h) boundary or above the 16kB (3FFFh) boundary so that it is unaffected by the memory modification.
The same precaution should be applied if the internal program memory size is modified while executing from external program memory.
For nonpage mode operations, off-chip memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2. While serving as a memory bus, these pins are not I/O ports. This convention follows the
standard 8051 method of expanding on-chip memory. Off-chip program memory access also occurs if the EA pin is
a logic 0. EA overrides all ROMSIZE bit settings. The PSEN signal goes active (low) to serve as a chip enable or
output enable when ports 0 and 2 fetch from external program memory.
The RD and WR signals are used to control the external data memory device. Data memory is accessed by MOVX
instructions. The MOVX@Ri instruction uses the value in the designated working register to provide the LSB of the address, while port 2 supplies the address MSB. The MOVX@DPTR instruction uses one of the two data pointers
to move data over the entire 64kB external data memory space. Software selects the data pointer used by writing to the SEL bit (DPS.0).
The DS89C430 also provides a user option for high-speed external memory access by reconfiguring the external memory interface into page mode operation.
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
fetch that takes four clocks. Page mode 1 is the only external addressing mode where the CPU does not require
stalls for external memory access, but page misses result in reduced external access performance.
On-Chip Program Memory
The processor can fetch the entire on-chip program memory range automatically. By default, the reset routines and all interrupt vectors are located in the lower 128 bytes of the on-chip program memory.
On-chip program memory is logically divided into pairs of 8kB, 16kB, or 32kB flash memory banks to support in-application programming. The on-chip program memory is designed to be programmed in-application with the
standard 5V VCC supply under the control of the user software or by using a built-in program memory loader. It can also be programmed in standard flash or EPROM programmers. The DS89C430 incorporates a memory management unit (MMU) and other hardware to support any of the three programming methods. The MMU controls
program and data memory access, and provides sequencing and timing controls for programming of the on-chip
program memory. A separate security flash block supports a standard three-level lock, a 64-byte encryption array, and other flash options. Security Features
The DS89C430 incorporates a 64-byte encryption array, allowing the user to verify program codes while viewing the data in encrypted form. The encryption array is implemented in a security flash memory block that has the
same electrical and timing characteristics as the on-chip program memory. Once the encryption array is programmed to non-FFh, the data presented in the verify mode is encrypted. Each byte of data is XNORed with a
byte in the encryption array during verification.
A three-level lock restricts viewing of the internal program and data memory contents. By programming the three
lock bits, the user can select a level of security as specified in Table 3.
Once a security level is selected and programmed, the setting of the lock bits remains. Only a mass erase can
erase these bits and allow reprogramming the security level to a less restricted protection.
Table 3. Flash Memory Lock Bits
The DS89C430 provides user-selectable options that must be set before beginning software execution. The option control register uses flash bits rather than SFRs, and is individually erasable and programmable as a byte-wide
register. Bit 3 of this register is defined as the watchdog POR. Setting this bit to 1 disables the watchdog reset function on power-up. Clearing this bit to 0 enables the watchdog reset function automatically. Other bits of this
register are undefined and are at logic 1 when read. The value of this register can be read at address FCh in parallel programming mode or executing a verify-option-control register instruction in ROM loader mode or in-
application programming mode.
The signature bytes can be read in ROM loader mode or in parallel programming mode. Reading data from
addresses 30h, 31h, and 60h provides signature information on manufacturer, part, and extension as follows:
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Note: The read/write accessibility of the flash memory during in-application programming is not affected by the
state of the lock bits. However, the lock bits do affect the read/write accessibility in ROM loader and parallel programming modes. In-Application Programming by User Software
The DS89C430 supports in-application programming of on-chip flash memory by user software. In-application programming is initiated by writing a flash command into the flash control (FCNTL:D5h) register to enable the flash
memory for erase/program/verify operations. Address and data are input into the MMU through the flash data
(FDATA:D6h) register. The flash command also enables read/write accesses to the FDATA. The MMUs sequencer provides the operation sequences and control functions to the flash memory. The MMU is designed to operate
independently from the processor, except for read/write access to the SFRs.
Only the upper bank of the on-chip program memory can be in-application programmed by the user software. The
lower bank of the on-chip program memory contains system hardware-dependent codes that are crucial to system operation and should not be altered during in-application programming.
All flash operations are self-timed. The user software can monitor the progress of an erase or programming operation through the flash busy (FBUSY;FCNTL.7) bit with a reset value at logic 1. A selected operation
automatically starts when required data is written to the FDATA SFR. The MMU clears the FBUSY bit to indicate
the start of a write/erase operation. The FBUSY bit may not change state for up to 1�s after the operation is requested. During this time, the application should poll the status of the FBUSY bit waiting for it to change state.
This bit is held low until either the end of the operation or until an error indicator is returned. A flash operating failure terminates the current operation and sets the flash error flag (FERR;FCNTL.6) to logic 1. Both the busy and
error flags are read-only bits.
Read/write access during in-application programming is not affected by the state of the lock bits.
A sample programming sequence for a "write upper program memory bank" is shown below. The command must be reentered each time an operation is requested, i.e., it is not permissible to issue the write upper program memory
bank command once and then repeatedly load address and data values to program a block of memory.
1. Make sure the FBUSY bit is 1 to indicate flash MMU is idle.
2. Write 0Bh to the FCNTL register using the timed access sequence.
3. Write address_MSB to the FDATA register.
4. Write address_LSB to the FDATA register.
5. Write data_value to the FDATA register.
6. Make sure the FBUSY bit is 0 to indicate programming has started.
7. Wait for FBUSY bit to return to 1 to indicate end of programming operation.
8. Make sure FERR is 0 to indicate no programming error.
The flash command (FC3FC0;FCNTL.3:0) bits provide flash commands as listed in Table 4.
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Table 4. In-Application Programming Commands
The flash command bits are cleared to 0 on all forms of reset, and it is important for the user software to clear
these bits to 0 to return the flash memory to read mode from erase/program operation. This setting is a no operation condition for the MMU, which allows the processor to return to its normal execution. Note that the busy
and error flags have no function in normal flash-read mode.
The FCNTL SFR can only be written using timed access. This procedure provides protection against inadvertent
erase/program operation on the flash memory. Any command written to the FCNTL during a flash operation is ignored (FBUSY = 0). To ensure data integrity, an erase command sequence should be reinitiated if an erase or
program operation is interrupted by a reset.
