DS89C420-ECL ,Ultra-high-speed microcontroller 80C52 compatible, 33 MHzfeatures 16kB of in-systemprogrammable flash memory, which can be programmed in-system from an I/O ..
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DS89C420-ECL-DS89C420QCL
Ultra-high-speed microcontroller 80C52 compatible, 33 MHz
GENERAL DESCRIPTIONThe DS89C420 offers the highest performance
available in 8051-compatible microcontrollers. Itfeatures a redesigned processor core that executes
every 8051 instruction (depending on the instruction
type) up to 12 times faster than the original for the
same crystal speed. Typical applications see a speedimprovement of 10 times using the same code and
crystal. The DS89C420 offers a maximum crystalspeed of 33MHz, achieving execution rates up to 33
million instructions per second (MIPS).
APPLICATIONSData LoggingVending
Automotive Test Equipment
Motor ControlMagstripe Reader/Scanner
Consumer Electronics
Gaming EquipmentAppliances (Washers, Microwaves, etc.)
TelephonesHVAC
Building Security and Door Access Control
Building Energy Control and ManagementUninterruptible Power Supplies
Programmable Logic Controllers
Industrial Control and Automation
ORDERING INFORMATION
Ordering information continued at end of data sheet.
FEATURES80C52 Compatible8051 Pin and Instruction-Set CompatibleFour Bidirectional I/O PortsThree 16-Bit Timer Counters256 Bytes Scratchpad RAMOn-Chip Memory16kB Flash MemoryIn-System Programmable through Serial Port1kB SRAM for MOVXROMSIZE FeatureSelects Internal Program Memory Size from
0 to 16kAllows Access to Entire External Memory
MapDynamically Adjustable By Software
See page 2 for a complete list of features.
PIN CONFIGURATIONS
DS89C420
Ultra-High-Speed Microcontroller
DS89C420
FEATURES80C52 compatible8051 pin and instruction-set compatibleFour bidirectional I/O portsThree 16-bit timer counters256 bytes scratchpad RAMOn-chip memory16kB flash memoryIn-system programmable through serialport1kB SRAM for MOVXROMSIZE featureSelects internal program memory size from0 to 16kAllows access to entire external memory
mapDynamically adjustable by softwareHigh-speed architecture1 clock-per-machine cycleDC to 33MHz operationSingle-cycle instruction in 30nsOptional variable length MOVX to accessfast/slow peripheralsDual data pointers with auto
increment/decrement and toggle selectSupports four paged modesPower Management ModeProgrammable clock dividerAutomatic hardware and software exitTwo full-duplex serial portsProgrammable watchdog timer13 interrupt sources (six external)Five levels of interrupt priorityPower-fail resetEarly warning power-fail interrupt
DETAILED DESCRIPTIONThe DS89C420 is pin compatible with all three packages of the standard 8051 and includes standard
resources such as three timer/counters, four 8-bit I/O ports, and a serial port. It features 16kB of in-system
programmable flash memory, which can be programmed in-system from an I/O port using a built-inprogram memory loader. It can also be loaded externally using standard commercially available
programmers.
Besides greater speed, the DS89C420 includes 1kB of data RAM, a second full-hardware serial port,
seven additional interrupts, two more levels of interrupt priority, programmable watchdog timer, brown-out monitor, and power-fail reset. The device also provides dual data pointers (DPTRs) to speed up
block-data memory moves. This feature is further enhanced with a new selectable automatic
increment/decrement and toggle-select operation. The speed of MOVX data memory access can be
adjusted by adding stretch values up to 10 machine cycle times for flexibility in selecting external
memory and peripherals.
A power management mode (PMM) significantly consumes less power by slowing the CPU execution
rate from 1 clock period per cycle to 1024 clock periods per cycle. A selectable switchback feature can
automatically cancel this mode to enable a normal speed response to interrupts.
The EMI reduction feature disables the ALE signal when the processor is not accessing external memory.
DS89C420
Figure 1. Block Diagram
DS89C420
Table 1. Pin Description
DS89C420
DS89C420
DS89C420
CompatibilityThe DS89C420 is a fully static CMOS 8051-compatible microcontroller similar to the DS87C520 in
functional features, but with much higher performance. In most cases the DS89C420 can drop into anexisting socket for the 8xC51 family to improve the operation significantly. While remaining familiar to
8051 family users, it has many new features. The DS89C420 runs the standard 8051 family instruction set
and is pin compatible with DIP, PLCC, and TQFP packages. In general, software written for existing
8051-based systems works without DS89C420 modification, with the exception of critical timing
routines, since the DS89C420 performs its instructions much faster than the original for any given crystalselection.
The DS89C420 provides three 16-bit timer/counters, two full-duplex serial ports, and 256 bytes of direct
RAM plus 1kB of extra MOVX RAM. I/O ports can operate as in standard 8051 products. Timers default
to a 12 clock-per-cycle operation to keep their timing compatible with original 8051 family systems.
However, timers are individually programmable to run at the new 1 clock-per-cycle if desired. The
DS89C420 provides several new hardware features implemented by new SFRs.
Performance OverviewThe DS89C420 features a completely redesigned high-speed 8051-compatible core and allows operationat a higher clock frequency, but the updated core does not have the dummy memory cycles that are
present in a standard 8051. A conventional 8051 generates machine cycles using the clock frequency
divided by 12. In the DS89C420, the same machine cycle takes 1 clock. Thus, the fastest instructions
execute 12 times faster for the same crystal frequency (and actually 24 times faster for the INC data
pointer instruction). It should be noted that this speed improvement reduces when using external memoryaccess modes that require more than 1 clock per cycle.
Improvement of individual programs depends on the actual instructions used. Speed-sensitive
applications make the most use of instructions that are 12 times faster. However, the sheer number of 12-
to-1 improved op codes makes dramatic speed improvements likely for any code. These architecture
improvements produce instruction cycle times as low as 30ns (33MIPs). The dual data pointer feature
also allows the user to eliminate wasted instructions when moving blocks of memory. The new pagemodes allow for increased efficiency in external memory accesses.
Instruction Set SummaryAll instructions perform the same functions as their 8051 counterparts. Their effect on bits, flags, and
other status functions is also identical. However, the timing of each instruction is different in both
absolute and relative number of clocks.
For absolute timing of real-time events, the timing of software loops can be calculated using informationin the “Instruction Set” table of the Ultra-High-Speed Flash Microcontroller User’s Guide. However,
counter/timers default to run at the older 12 clocks per increment. In this way, timer-based events occur at
the standard intervals with software executing at higher speed. Timers optionally can run at lower
numbers of clocks per increment to take advantage of faster processor operation.
The relative time of some instructions might be different in the new architecture than it was previously.
For example, in the original architecture, the “MOVX A, @DPTR” instruction and the “MOV direct,
direct” instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the sameamount of time. In the DS89C420, the MOVX instruction takes as little as two machine cycles or two
oscillator cycles but the “MOV direct, direct” uses three machine cycles or three oscillator cycles. While
DS89C420
execution. The user concerned with precise program timing should examine the timing of each instruction
to become familiar with the changes.
Special Function Registers (SFRs)All peripherals and operations that are not explicit instructions in the DS89C420 are controlled through
SFRs. The most common features basic to the architecture are mapped to the SFRs. These include the
CPU registers (ACC, B, and PSW), data pointers (DPTRs), stack pointer, I/O ports, timer/counters, and
serial ports. In many cases, an SFR controls an individual function or reports the function’s status. TheSFRs reside in register locations 80h–FFh and are only accessible by direct addressing. SFRs whose
addresses end in 0h or 8h are bit-addressable.
All standard SFR locations from the 8051 are duplicated in the DS89C420 and several SFRs have been
added for the unique features of the DS89C420. Most of these features are controlled by bits in SFRs
located in unused locations in the 8051 SFR map. This allows for increased functionality while
maintaining complete instruction set compatibility. Table 2 summarizes the SFRs and their locations.Table 3 specifies the default reset condition for all SFR bits.
Data PointersThe data pointers (DPTR and DPTR1) are used to assign a memory address for the MOVX instructions.
This address can point to a MOVX RAM location (on-chip or off-chip), or a memory-mapped peripheral.
Two pointers are useful when moving data from one memory area to another, or when using a memory-
mapped peripheral for both source and destination addresses. The user selects the active pointer through adedicated SFR bit (Sel = DPS.0), or activates an automatic toggling feature for altering the pointer
selection (TSL = DPS.5). An additional feature, if selected, provides automatic incrementing or
decrementing of the current DPTR.
Stack PointerThe stack pointer denotes the register location at the top of the stack, which is the last used value. Theuser can place the stack anywhere in the scratchpad RAM by setting the stack pointer to the desired
location, although the lower bytes are normally used for working registers.
I/O PortsThe DS89C420 offers four 8-bit I/O ports. Each I/O port is represented by an SFR location, and can be
written or read. The I/O port has a latch that contains the value written by software.
Counter/TimersThree 16-bit timer/counters are available in the DS89C420. Each timer is contained in two SFR locations
that can be read or written by software. The timers are controlled by other SFRs described in the “SFR
Bit Description” section of the Ultra-High-Speed Flash Microcontroller User’s Guide.
Serial PortsThe DS89C420 provides two UARTs that are controlled and accessed by SFRs. Each UART has anaddress that is used to read and write the UART. The same address is used for both read and write
operations, and the read and write operations are distinguished by the instruction. Each UART is
controlled by its own SFR control register.
DS89C420
Table 2. Special Function Registers
DS89C420
DS89C420
Table 3. SFR Reset Value
DS89C420
DS89C420
Memory OrganizationThere are three distinct memory areas in the DS89C420: scratchpad registers, program memory, and data
memory. All registers are located on-chip but the program and data memory spaces can be either on-chip,
off-chip, or both. There are 16kB of on-chip program memory implemented in flash memory and 1kB of
on-chip data memory space that can be configured as program space using the PRAME bit in the
ROMSIZE feature. The DS89C420 uses a memory-addressing scheme that separates program memory
from data memory. The program and data segments can be overlapped since they are accessed in different
ways. If the maximum address of on-chip program or data memory is exceeded, the DS89C420 performs
an external memory access using the expanded memory bus. The PSEN signal goes active low to serve
as a chip enable or output enable when performing a code fetch from external program memory. MOVX
instructions activate the RD or WR signal for external MOVX data memory access. The lower 128
bytes of on-chip flash memory store reset and interrupt vectors. The program memory ROMSIZE feature
allows software to dynamically configure the maximum address of on-chip program memory. This allows
the DS89C420 to act as a bootloader for an external flash or NV SRAM. It also enables the use of the
overlapping external program spaces.
256 bytes of on-chip RAM serve as a register area and program stack, which are separated from the data
memory.
Register SpaceRegisters are located in the 256 bytes of on-chip RAM, which can be divided into two subareas of 128
bytes each as illustrated in Figure 2. Separate classes of instructions are used to access the registers and
the program/data memory. The upper 128 bytes are overlapped with the 128 bytes of SFRs in the memory
map. The upper 128 bytes of scratchpad RAM are accessed by indirect addressing, and the SFR area is
accessed by direct addressing. The lower 128 bytes can be accessed by direct or indirect addressing.
There are four banks of eight individual working registers in the lower 128 bytes of scratchpad RAM.
The working registers are general-purpose RAM locations that can be addressed within the selected bank
by any instructions that use R0–R7. The register bank selection is controlled through the program status
register in the SFR area. The contents of the working registers can be used for indirectly addressing the
upper 128 bytes of scratchpad RAM.
To support the Boolean operations, there are individually addressable bits in both the RAM and SFR
areas. In the scratchpad RAM area, registers 20h–2Fh are bit-addressable by software using Boolean
operation instructions.
Another use of the scratchpad RAM area is for the stack. The stack pointer in the SFRs is used to select
storage locations for program variables and for return addresses of control operations.
DS89C420
Figure 2. Memory Map
DS89C420
Memory ConfigurationAs illustrated in Figure 2, the DS89C420 incorporates two 8kB flash memories for on-chip program
memory and 1kB of SRAM for on-chip data memory or a particular range (400–7FF) of “alternate”program memory space. The DS89C420 uses an address scheme that separates program memory from
data memory, such that the 16-bit address bus can address each memory area up to 64kB.
Program Memory AccessOn-chip program memory begins at address 0000h and is contiguous through 3FFFh (16kB). Exceeding
the maximum address of on-chip program memory causes the device to access off-chip memory.
However, the maximum on-chip decoded address is selectable by software using the ROMSIZE feature.Software can cause the DS89C420 to behave like a device with less on-chip memory. This is beneficial
when overlapping external memory is used. The maximum memory size is dynamically variable. Thus, a
portion of memory can be removed from the memory map to access off-chip memory, then be restored to
access on-chip memory. In fact, all of the on-chip memory can be removed from the memory map
allowing the full 64kB memory space to be addressed from off-chip memory. Program memory addressesthat are larger than the selected maximum are automatically fetched from outside the part through ports 0
and 2 (Figure 2).
The ROMSIZE register is used to select the maximum on-chip decoded address for program memory.
Bits RMS2, RMS1, RMS0 have the following effect:
The reset default condition is a maximum on-chip program-memory address of 16kB. When accessingexternal program memory, the first 16kB would be inaccessible. To select a smaller effective program
memory size, software must alter bits RMS2–RMS0. Altering these bits requires a timed access
procedure as explained later.
Care should be taken so that changing the ROMSIZE register does not corrupt program execution. Forexample, assume that a DS89C420 is executing instructions from internal program memory near the
12kB boundary (~3000h) and that the ROMSIZE register is currently configured for a 16kB internal
program space. If software reconfigures the ROMSIZE register to 4kB (0000h–0FFFh) in the current
state, the device immediately jumps to external program execution because program code from 4kB to
16kB (1000h–3FFFh) is no longer located on-chip. This could result in code misalignment and executionof an invalid instruction. The recommended method is to modify the ROMSIZE register from a location
in memory that is internal (or external) both before and after the operation. In the above example, the
instruction that modifies the ROMSIZE register should be located below the 4kB (1000h) boundary or
above the 16kB (3FFFh) boundary so that it is unaffected by the memory modification. The same
DS89C420
For non-page mode operations, off-chip memory is accessed using the multiplexed address/data bus onP0 and the MSB address on P2. While serving as a memory bus, these pins are not I/O ports. This
convention follows the standard 8051 method of expanding on-chip memory. Off-chip program memory
access also occurs if the EA pin is a logic 0. EA overrides all bit settings. The PSEN signal goes active
(low) to serve as a chip enable or output enable when port 0 and port 2 fetch from external program
memory.
The RD and WRsignals are used to control the external data memory device. Data memory is accessedby MOVX instructions. The MOVX@Ri instruction uses the value in the designated working register to
provide the LSB of the address, while port 2 supplies the address MSB. The MOVX@DPTR instruction
uses one of the two data pointers to move data over the entire 64kB external data memory space.
Software selects the data pointer to be used by writing to the SEL bit (DPS.0).
The DS89C420 also provides a user option for high-speed external memory access by reconfiguring the
external memory interface into page mode operation.
Note: When using the original 8051 expanded bus structure, the throughput is reduced by 75% comparedwith that of internal operations. This is due to the CPU being stalled for three out of four clocks waitingfor the data fetch, which takes four clocks. Page Mode 1 is the only external addressing mode where the
CPU does not require stalls for external memory access, but page misses result in reduced external access
performance.
On-Chip Program MemoryThe full on-chip program memory range can be fetched by the processor automatically. The reset routinesand all interrupt vectors are located in the lower 128 bytes of the on-chip program memory area.
On-chip program memory is logically divided into two 8kB flash memory banks and is designed to be
programmed with the standard 5V VCC supply by using a built-in program memory loader. It can also be
programmed in standard flash or EPROM programmers. The DS89C420 incorporates a memorymanagement unit (MMU) and other hardware to support any of the two programming methods. The
MMU controls program and data memory access, and provides sequencing and timing controls for
programming the on-chip program memory. There is also a separate security flash block that is used to
support a standard three-level lock, a 64-byte encryption array, and other flash options.
Security FeaturesThe DS89C420 incorporates a 64-byte encryption array, allowing the user to verify program codes whileviewing the data in encrypted form. The encryption array is implemented in a security flash memory
block that has the same electrical and timing characteristics as the on-chip program memory. Once the
encryption array is programmed to non-FFh, the data presented in the verify mode is encrypted. Each
byte of data is XNOR’ed with a byte in the encryption array during verification.
A three-level lock restricts viewing of the internal program and data memory contents. By programming
the three lock bits, the user can select a level of security as specified in Table 4. Once a security level is
selected and programmed, the setting of the lock bits remains. Only a mass erase can erase these bits to
allow reprogramming the security level to a less restricted protection.
DS89C420
Table 4. Flash Memory Lock BitsThe DS89C420 provides user-selectable options that must be set before beginning software execution.
The option control register uses flash bits rather than SFRs, and is individually erasable andprogrammable as a byte-wide register. Bit 3 of this register is defined as the watchdog POR default.
Setting this bit to 1 disables the watchdog reset function on power-up, and clearing this bit to 0 enables
the watchdog reset function automatically. Other bits of this register are undefined and are at logic 1
when read. The value of this register can be read at address FCh in parallel programming mode or when
executing a verify-option control-register instruction in ROM loader mode.
The signature bytes can be read in ROM loader mode or in parallel programming mode. Reading data
from addresses 30h, 31h, and 60h provides signature information about manufacturer, part, and extension
as follows:
ROM LoaderThe full 16kB of on-chip flash program-memory space, security flash block, and external SRAM can be
programmed in-system from an external source through serial port 0 under the control of a built-in ROMloader. The ROM loader also has an auto-baud feature that determines which baud rate frequencies are
being used for communication and sets up the baud rate generator for communication at that frequency.
When the DS89C420 is powered up and has entered its user operating mode, the ROM loader mode can
be invoked at any time by forcing RST = 1, EA = 0, and PSEN = 0. It remains in effect until power-
down or when the condition (RST = 1 and PSEN = EA = 0) is removed. Entering the ROM loader mode
forces the processor to start fetching from the 2kB internal ROM for program memory initialization andother loader functions.
The read/write accessibility is determined by the state of the lock bits, which can be verified directly by
the ROM loader. In the ROM loader mode, a mass-erase operation also erases the memory bank select
DS89C420
Flash programming is executed by a series of internal flash commands that are derived (by the built-inROM loader) from data transmitted over the serial interface from a host PC. PC-based software tools that
configure and load the microcontrollers are available at /micros/ftpinfo.html.
Full details of the ROM loader software and its implementation are given in the Ultra-High-Speed Flash
Microcontroller User’s Guide.
Figure 3. Interfacing the Bootloader to a PC
DS89C420
Parallel ProgrammingThe DS89C420 allows parallel programming of its internal flash memory compatible with standard flash
or EPROM programmers. In parallel programming mode, a mass-erase command is used to erase allmemory locations in the 16kB program memory, the security block, and the memory bank select. Erasing
the memory bank select sets it to the default state; the memory bank select cannot be altered otherwise. If
lock bit LB2 has not been programmed, the program code can be read back for verification. The state of
the lock bits can also be verified directly in the parallel programming mode. One instruction is used to
read signature information (at addresses 30, 31, and 60h). Separate instructions are used for the optioncontrol register.
The following sequence can be used to program the flash memory in the parallel programming mode:
1) The DS89C420 is powered up and running at a clock speed between 4MHz and 6MHz.
2) Set RST = EA = 1 and PSEN = 0.
3) Apply the appropriate logic combination to pins P2.6, P2.7, P3.6, and P3.7 to select one of the flash
instructions shown in Table 8.For program operation, apply the desired address to pins P1.7:0 and P2.5:0. Data is written to
port 0.For verify operation, apply the desired address to pins P1.7:0 and P2.5:0. Data is read at port 0.
4) Pulse ALE/PROGonce to perform an erase/program operation.
5) Repeat steps 3 and 4 as necessary.
DS89C420
Table 5. Parallel Programming Instruction Set Mass erase requires an active-low PROGpulse width of 828ms. Erase option control register requires an active-low PROGpulse width of 828ms. Byte program requires an active-low PROGpulse width of 100�s max.
PROG is weakly pulled to a high internally.
Note 1: P3.2 is pulled low during programming to indicate Busy. P3.2 is pulled high again when programming is completed to indicate Ready.
Note 2: P3.0 is pulled high during programming to indicate an error.
DS89C420
On-Chip MOVX Data MemoryOn-chip data memory is provided by the 1kB SRAM and occupies addresses 0000h through 03FFh. The
internal data memory is disabled after a power-on reset, and any MOVX instruction directs the datamemory access to the external data memory. To enable the internal data memory, software must
configure the data memory enable bits DME1 and DME0 (PMR.1-0). See “SFR Bit Descriptions” in the
Ultra-High-Speed Flash Microcontroller User’s Guide for data memory configurations. Once enabled,
MOVX instructions with addresses inside the 1k range access the on-chip data memory, and addresses
exceeding the 1k range automatically access external data memory.
An internal data memory cycle spans only one system clock period to support fast internal execution.
Data Pointer Increment/Decrement and OptionsThe DS89C420 incorporates a hardware feature to assist applications that require data pointer
increment/decrement. Data pointer increment/decrement bits ID0 and ID1 (DPS.6 and DPS.7) define how
the INC DPTR instruction functions in relation to the active DPTR (selected by the SEL bit). SettingID0 = 1 and SEL = 0 enables the decrement operation for DPTR, and execution of the INC DPTR
instruction decrements the DPTR contents by 1. Similarly, setting ID1 = 1 and SEL = 1 enables the
decrement operation for DPTR1, and execution of the INC DPTR instruction decrements the DPTR1
contents by 1. With this feature, the user can configure the data pointers to operate in four ways for the
INC DPTR instruction:
The active data pointer is always selected by the SEL (DPS.0) bit. The DS89C420 offers a programmable
option that allows any instructions related to data pointer to toggle the SEL bit automatically. This optionis enabled by setting the toggle-select-enable bit (TSL-DPS.5) to a logic 1. Once enabled, the SEL bit is
automatically toggled after the execution of one of the following five DPTR-related instructions:
INC DPTRMOV DPTR #data16MOVC A, @A+DPTRMOVX A, @DPTR
MOVX @DPTR, A
The DS89C420 also offers a programmable option that automatically increases (or decreases) the
contents of the selected data pointer by 1 after the execution of a DPTR-related instruction. The actual
function (increment or decrement) is dependent upon the setting of the ID1 and ID0 bits. This option is
enabled by setting the automatic increment/decrement enable (AID-DPS.4) to a logic 1 and is affected byone of the following three instructions:
MOVC A, @A+DPTRMOVX A, @DPTRMOVX @DPTR, A
DS89C420
External MemoryThe DS89C420 executes external memory cycles for code fetches and read/writes of external program
and data memory. A non-page external memory cycle is four times slower than the internal memorycycles (i.e., an external memory cycle contains four system clocks)*. However, a page mode external
memory cycle can be completed in 1, 2, or 4 system clocks for a page hit and 2, 4, or 8 system clocks for
a page miss, depending on user selection. The DS89C420 also supports a second page mode operation
with a different external bus structure that provides for fast external code fetches but uses 4 system clock
cycles for data memory access.
*For this reason, although a DS89C420 can be substituted for a ROM-less 8051 device (DS80C310,
C320, etc.), there is no increase in execution speed.
External Program Memory Interface (Non-Page Mode)Figure 4 shows the timing relationship for internal and external code fetches when CD1 and CD0 are set
to 10b, assuming the microcontroller is in non-page mode for external fetches. Note that an externalprogram fetch takes 4 system clocks, and an internal program fetch requires only 1 system clock.
As illustrated in Figure 4, ALE is deasserted when executing an internal memory fetch. The DS89C420
provides a programmable user option to turn on ALE during internal program memory operation. ALE is
automatically enabled for code fetch externally, independent of the setting of this option.
PSEN is only asserted for external code fetches, and is inactive during internal execution.
Figure 4. External Program Memory Access (Non-Page Mode and
CD1:CD0 = 10)
DS89C420
External Data Memory Interface in Non-Page Mode OperationJust like the program memory cycle, the external data memory cycle is four times slower than the internal
data memory cycle in non-page mode. A basic internal memory cycle contains one system clock and abasic external memory cycle contains four system clocks for non-page mode operation.
The DS89C420 allows software to adjust the speed of external data memory access by stretching the
memory bus cycle. CKCON (8Eh) provides an application-selectable stretch value for this purpose.
Software can change the stretch value dynamically by changing the setting of CKCON.2–CKCON.0.Table 6 shows the data memory cycle stretch values and their effects on the external MOVX-memory bus
cycle and the control signal pulse width in terms of the number of oscillator clocks. A stretch machine
cycle always contains four system clocks.
Table 6. Data Memory Cycle Stretch ValuesAs shown in Table 6, the stretch feature supports eight stretched external data-memory access cycles that
can be categorized into three timing groups. When the stretch value is cleared to 000b, there is no stretch
on external data memory access and a MOVX instruction is completed in two basic memory cycles.
When the stretch value is set to 1, 2, or 3, the external data-memory access is extended by 1, 2, or 3
stretch machine cycles, respectively. Note that the first stretch value does not result in adding four system
clocks to the RD/WR control signals. This is because the first stretch uses one system clock to create
additional setup time and one system clock to create additional address hold time. When using very slow
RAM and peripherals, a larger stretch value (4–7) can be selected. In this stretch category, one stretch
machine cycle (4 system clocks) is used to stretch the ALE pulse width, one stretch machine cycle is used
to create additional setup, one stretch machine cycle is used to create additional hold time, and one stretch
machine cycle is added to the RD or WR strobes.
Figures 5 and 6 illustrate the timing relationship for external data-memory access in full speed (stretch
value = 0), in the default stretch setting (stretch value =1), and slow data-memory accessing
(stretch value = 4) when the system clock is in divide by one mode (CD1:CD0 = 10b).
DS89C420
Figure 5. Non-Page Mode, External Data-Memory Access (Stretch = 0,
CD1:CD2 = 10)
Figure 6. Non-Page Mode, External Data-Memory Access (Stretch = 1,
CD1:CD2 = 10)
DS89C420
Page Mode, External Memory CyclePage mode retains the basic circuitry requirement for original 8051 external memory interface, but alters
the configuration of P0 and P2 for the purposes of address output and data I/O during external memory
cycles. Additionally, the functions of ALE and PSEN are altered to support this mode of operation.
Page mode is enabled by setting the PAGEE (ACON.7) bit to a logic 1. Clearing the PAGEE bit to a
logic 0 disables the page mode and the external bus structure defaults to the original 8051 expanded bus
configuration (non-page mode). The DS89C420 supports page mode in two external bus structures. The
logic value of the page mode select bits in the ACON register determines the external bus structure and
the basic memory cycle in the number of system clocks. Table 7 summarizes this option. The first three
selections use the same bus structure but with a different memory cycle time. Setting the select bits to 11b
selects another bus structure. Write access to the ACON register requires a timed access.
Table 7. Page Mode Select
DS89C420
The first page mode (page mode 1) external bus structure uses P2 as the primary address bus,
(multiplexing both the most significant byte (MSB) and least significant byte (LSB) of the address foreach external memory cycle) and P0 is used as the primary data bus. During external code fetches, P0 is
held in a high-impedance state by the processor. Op codes are driven by the external memory onto P0 and
latched at the end of the external fetch cycle at the rising edge of PSEN. During external data read/write
operations, P0 functions as the data I/O bus. It is held in a high-impedance state for external reads from
data memory, and driven with data during external writes to data memory.A page miss occurs when the MSB of the subsequent address is different from the last address.
The external memory machine cycle can be 2, 4, or 8 system clocks in length for a page miss.A page hit occurs when the MSB of the subsequent address does not change from the last address.
The external memory machine cycle can be 1, 2, or 4 system clocks in length for a page hit.
During a page hit, P2 drives Addr0–7 of the 16-bit address while the most significant address byte is held
in the external address latches. PSEN, RD, and WR strobe accordingly for the appropriate operation on
the P0 data bus. There is no ALE assertion for page hits.
During a page miss, P2 drives the Addr [8:15] of the 16-bit address and holds it for the duration of the
first half of the memory cycle to allow the external address latches to latch the new most significant
address byte. ALE is asserted to strobe the external address latches. During this operation, PSEN, RD,
and WR are all held in inactive states and P0 is in a high-impedance state. The second half of the
memory cycle is executed as a page-hit cycle and the appropriate operation takes place.
A page miss can occur at set intervals or during external operations that require a memory access into a
page of memory that has not been accessed during the last external cycle. Generally, the first external
memory access causes a page miss. The new page address is stored internally, and is used to detect a page
miss for the current external memory cycle.
Note that there are a few exceptions for this mode of operation when PAGES1 and PAGES2 are set to
00b:PSEN is asserted for both page hit and page miss for a full clock cycle.The execution of external MOVX instruction causes a page miss.A page miss occurs when fetching the next external instruction following the execution of an external
MOVX instruction.
Figure 7 shows the external memory cycle for this bus structure. The first case illustrates a back-to-back
execution sequence for 1-cycle page mode (PAGES1 = PAGES0 = 0b). PSEN remains active during
page hit cycles, and page misses are forced during and after MOVX executions, independent of the most
significant byte of the subsequent addresses. The second case illustrates a MOVX execution sequence for
2-cycle page mode (PAGES1 = 0 and PAGES0 = 1). PSEN is active for a full clock cycle in code
fetches. Note that the page misses in this sequence are caused by changing the MSB of the data address.
The third case illustrates a MOVX execution sequence for 4-cycle page mode (PAGES1 = 1 and
DS89C420
The second page mode (page mode 2) external bus structure multiplexes the most significant address byte
with data on P2, and uses P0 for the least significant address byte. This bus structure is used to speed up
external code fetches only. External data-memory access cycles are identical to the non-page mode except
for the different signals on P0 and P2. Figure 8 illustrates the memory cycle for external code fetches.
Figure 7. Page Mode 1, External Memory Cycle (CD1:CD0 = 10)
DS89C420
Figure 8. Page Mode 2, External Code Fetch Cycle (CD1:CD0 = 10)
Stretch External Data Memory Cycle in Page ModeThe DS89C420 allows software to adjust the speed of external data memory access by stretching thememory bus cycle in page mode operation just like non-page mode operation. The following tables
summarize the stretch values and their effects on the external MOVX-memory bus cycle and the control
signals’ pulse width in terms of the number of oscillator clocks. A stretch machine cycle always contains
four system clocks, independent of the logic value of the page mode select bits.
Table 8. Page Mode 1, Data Memory Cycle Stretch Values
(Pages1:Pages0 = 00)
DS89C420
Table 9. Page Mode 1, Data Memory Cycle Stretch Values
(Pages1:Pages0 = 01)
Table 10. Page Mode 1, Data Memory Cycle Stretch Values
(Pages1:Pages0 = 10)
DS89C420
Table 11. Page Mode 2, Data Memory Cycle Stretch Values
(Pages1:Pages0 = 11)As shown in the previous tables, the stretch feature supports eight stretched external data-memory access
cycles that can be categorized into three timing groups. When the stretch value is cleared to 000b, there is
no stretch on external data-memory access and a MOVX instruction is completed in two basic memorycycles. When the stretch value is set to 1, 2, or 3, the external data memory access is extended by 1, 2, orstretch memory cycles, respectively. Note that the first stretch value does not result in adding four
system clocks to the control signals. This is because the first stretch uses one system clock to create
additional address setup and data bus float time, and one system clock to create additional address and
data hold time. When using very slow RAM and peripherals, a larger stretch value (4–7) can be selected.In this stretch category, two stretch cycles are used to create additional setup (the ALE pulse width is also
stretched by one stretch cycle for page miss) and one stretch cycle is used to create additional hold time.
The following timing diagrams illustrate the external data-memory access at divide by 1 system clock
mode (CD1:CD0 = 10b).
