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DS8906N
AM/FM Digital Phase-Locked Loop Synthesizer
TL/F/5775
DS8906
AM/FM
Digital
Phase-Locked
Loop
Synthesizer
July 1986
DS8906 AM/FM Digital Phase-Locked Loop Synthesizer
General Description
The DS8906isa PLL synthesizer designed specificallyfor
usein AM/FM radios.It containsthe reference oscillator,a
phase comparator,a charge pump,a 120 MHz ECL/I2L
dual modulus programmable divider,anda 20-bit shift regis-
ter/latchfor serial data entry. The deviceis designedto
operate witha serial data controller generatingthe neces-
sary division codesfor each frequency,and logic stateinfor-
mationfor radio function inputs/outputs.
The Colpitts reference oscillatorforthe PLL operatesat4
MHz.A chainof dividersis usedto generatea 500 kHz
clock signalforthe external controller. Additional dividers
generatea 12.5kHz reference signalforFManda500Hz
reference signalfor AM/SW.Oneof these reference signals selectedbythe data fromthe controllerforusebythe
phase comparator. Additional dividersare usedto generate50Hz timing signal usedbythe controllerfor ‘‘time-of-
day’’.
Datais transferred betweenthe frequency synthesizerand
the controllerviaa3 wirebus system. This consistsofa
data input line,an enablelineanda clock line. Whenthe
enablelineis low, datacanbe shifted fromthe controller
intothe frequency synthesizer. Whenthe enablelineis tran-
sitioned fromlowto high, data entryis disabled and data
presentinthe shift registeris latched.
Fromthe controller 22-bit data stream,the first2bitsad-
dressthe device permitting other devicesto share thesame
bus.Ofthe remaining 20-bit data word,the next 14-bitsare
usedforthePLL divide code.The remaining6bitsare con-
nectedvia latchesto output pins. These6bitscanbe used drive radio functions suchas gain, mute, FM,AM,LWand only. These outputsare open collector.Bit18is used
internallyto selecttheAMorFM local oscillator input andto
select betweenthe500Hzand 12.5kHz reference.A high
levelatbit18 indicatesFMandalow level indicates AM.
The PLL consistsofa 14-bit programmableI2L divider,an
ECL phase comparator,an ECL dual modulus (p/pa1)
prescaler,anda high speed charge pump. The programma-
ble divider dividesby (Na1),N beingthe number loaded
intothe shift register (bits 1–14 after address).Itis clockedtheAM input viaan ECLd7/8 prescaler,orthroughad
63/64 prescaler fromtheFM input. TheAM inputwill work frequenciesupto8 MHz, whiletheFM input worksupto
120 MHz.TheAM bandis tuned witha frequency resolution 500HzandtheFM bandis tunedwitha resolutionof 12.5
kHz. The bufferedAM andFM inputsare self-biasedand
canbe driven directly bythe VCOthrua capacitor.The ECL
phase comparator produces very accurate resolutionofthe
phase difference betweenthe input signalandthe reference
oscillator.
The high speed charge pump consistsofa switchable con-
stant current source (b0.3 mA) anda switchable constant
current sink (a0.3 mA).Ifthe VCO frequencyis low,the
charge pumpwill source current,andsink current ifthe VCO
frequencyis high. separate VCCMpin (typically drawing1.5 mA) powersthe
oscillatorand reference chainto provide controller clocking
frequencies whenthe balanceofthe PLLis powered down.
Features Uses inexpensive4 MHz reference crystal FIN capability greater than 120 MHz allows direct syn-
thesisatFM frequenciesFM resolutionof 12.5 kHz allows usageof 10.7 MHz
ceramic filter distribution Serial data entryfor simplified control50Hz outputfor ‘‘time-of-day’’ reference with separate
low power supply (VCCM) 6-open collector buffered outputsfor band switching
and other radio functions SeparateAMandFM inputs.AM inputhas15mV (typi-
cal) hysteresis
Connection Diagram
Dual-In-Line Package
TL/F/5775–1
TopView
OrderNumber DS8906N
SeeNS Package Number N20A
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorp.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
