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DS8800HN/a1avaiDS8800H / A+ / DS7800
DS8800HNSCN/a117avaiDS8800H / A+ / DS7800


DS8800H ,DS8800H / A+ / DS7800o o 8 Absolute Maximum RatlngS(Note1) Operating Conditions h' If MltltaryfAerospatre speclfled d ..
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DS8830J ,Dual Differential Line DriverElectrical Characteristics (Notes 3, 4)Symbol Parameter Conditions Min Typ Max UnitsV Logical “1” I ..
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DS8800H
DS8800H / A+ / DS7800
',' Absolute Maximum Ratings (Note 1) Operating Conditions
8 If Mllltary/Aerospace specified devices are required, Min Max Unlts
3 please contact the National Semiconductor Sales Supply Voltage, Vcc
3 Ofllee/Dlstrlbutors for availability and speeifleattons. DS7800 4.5 5.5 v
IN Voc Supply Voltage 7.0V DS8800 4.75 5.25 V
8 V2 Supply Voltage - 30V Temperature (TA) tt
V3 Supply Voltage 30V 3:23:33 1:55 :17205 O:
V3-V2 Voltage Differential 40V
Input Voltage 5.5V
Storage Temperature - 65°C to + 150'C
Lead Temperature (Soldering, 4 seconds) 260''C
Maximum Power Dissipation' at 25°C
Metal Can (TO-5) Package 690 mW
‘Derate metal can package 4.6 m1N/'C above 25''C
Electrical Characteristics (Notes 2 and 3)
(Note 6)
. l 's: W _
Symbol Parameter Conditions Min Max Units
't's-l")-c,
Theory of Operation
The two input diodes perform the AND function on TTL in-
put voltage levels. When at least one input voltage is a logi-
cal "o", current from Vcc (nominally 5.0V) passes through
R1 and out the input(s) which is at the low voltage. Other
than small leakage currents, this current drawn from Vcc
through the 20 kn resistor is the only source of power dissi-
pation in the logical "I'' output state.
When both inputs are at logical "l" levels, current passes
through R, and diverts to transistor th, turning it on and
thus pulling current through Ra. Current is then supplied to
the PNP transistor, th. The voltage losses caused by cur-
rent through Q1, Ds and th necessitate that node P reach a
voltage sufficient to overcome these losses before current
begins to flow. To achieve this voltage at node P, the inputs
must be raised to a voltage level which is one diode poten-
tial lower than node P. Since these levels are exactly the
same as those experienced with conventional TTL, the in-
terfacing with these types of circuits is achieved.
Transistor th provides "constant current switching" to the
output due to the common base connection of th. When at
least one input is at the logical "o" level, no current is deliv-
ered to th; so that its collector supplies essentially zero
current to the output stage. But when both inputs are raised
to a logical "I" level current is supplied to th.
Selecting Power Supply Voltage
The graph shows the boundary conditions which must be
used for proper operation of the unit. The range of operation
for power supply V2 is shown on the X axis. It must be
between ~25v and -8V. The allowable range for power
supply V3 is governed by supply V2. With a value chosen for
V2, Va may be selected as any value along a vertical line
passing through the Va value and terminated by the bounda-
ries of the operating region. A voltage difference between
power supplies of at least 5V should be maintained for ade-
quate signal swing.
Switching Time Waveforms
01lTFOT--
Since this current is relatively constant, the collector of th
acts as a constant current source for the output stage. Logic
inversion is performed since logical "I" input voltages
cause current to be supplied to th and th. And when ck,
turns on the output voltage drops to the logical "0" level.
The reason for the PNP current source, th, is so that the
output stage can be driven from a high impedance. This
allows voltage V2 to be adjusted in accordance with the
application. Negative voltages to -25V can be applied to
V2. Since the output will neither source nor sink large
amounts of current, the output voltage range is almost ex-
clusively dependent upon the values selected for V2 and V3.
Maximum leakage current through the output transistor th
is specified at 10 MA under worst-Cass voltage between V2
and V3. This will result in a logical "I" output voltage which
is 0.2V below V3. Likewise the clamping action of diodes Da,
Ds and Ds prevents the logical "0" output voltage from
falling lower than 2V above Va, thus establishing the ouput
voltage swing at typically 2 volts less than the voltage sepa-
ration between V2 and Va,
OPE RATING
TL/F/5827-5
TLIF/5827-6
008880/008130
This datasheet has been :
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National Semiconductor was acquired by Texas Instruments.
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