DS87C550-QNL ,EPROM High-Speed Micro with A/D and PWMfeatures 8 kbytes of EPROM with anextra 1 kbyte of data RAM (in addition to the 256 bytes of scratc ..
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DS8820AN ,Dual Line ReceiverGeneral Description70˚C respectively), over the entire input voltage range, forThe DS7820A and the ..
DS8830J ,Dual Differential Line DriverElectrical Characteristics (Notes 3, 4)Symbol Parameter Conditions Min Typ Max UnitsV Logical “1” I ..
DS8830J ,Dual Differential Line DriverDS7830/DS8830 Dual Differential Line DriverMarch 1992DS7830/DS8830Dual Differential Line Driver
DS87C550KCL-DS87C550QCL-DS87C550-QNL
EPROM High-Speed Micro with A/D and PWM
FEATURES 87C52-Compatible- 8051 pin- and instruction set-compatibleThree 16-bit timer/counters- 256 bytes scratchpad RAM
On-chip Memory- 8 kbytes EPROM (OTP & Windowed Packages)1 kbyte extra on-chip SRAM for MOVX access
On-chip Analog to Digital Converter- Eight channels of analog input, 10-bit resolution- Fast conversion timeSelectable internal or external reference voltage
Pulse Width Modulator Outputs- Four channels of 8-bit PWMChannels cascadable to 16-bit PWM§
4 Capture + 3 Compare Registers 55 I/O Port Pins New Dual Data Pointer Operation- Either data pointer can be incremented or
decremented§
ROMSIZE FeatureSelects effective on-chip ROM size from 0 to 8k- Allows access to entire external memory mapDynamically adjustable by software§
High-Speed Architecture4 clocks/machine cycle (8051 = 12)- Runs DC to 33 MHz clock ratesSingle-cycle instruction in 121 ns-
New Stretch Cycle feature allows access to
fast/slow memory or peripherals§
Unique Power Savings Modes EMI Reduction Mode disables ALE when notneeded
High integration controller includes:Power-fail reset- Early-warning power-fail interrupt
Two full-duplex hardware serial ports- Programmable watchdog timer§ 16 total interrupt sources with 6 external
Available in 68-pin PLCC, 80-pin PQFP, and68-pin windowed CLCC
PIN ASSIGNMENT
EPROM High-Speed
Micro with A/D and PWM16143
68-Pin PLCC
68-Pin WINDOWED CLCC2580
DALLAS
DS87C55080-Pin PQFP
DS87C550
DESCRIPTIONThe DS87C550 EPROM High-Speed Micro with A/D and PWM is a member of the fastest 100% 8051-compatible microcontroller family available. It features a redesigned processor core that removes wasted
clock and memory cycles. As a result, it executes 8051 instructions up to three times faster than the
original architecture for the same crystal speed. The DS87C550 also offers a maximum crystal speed of
33 MHz, resulting in apparent execution speeds of up to 99 MHz.
The DS87C550 uses an industry standard 8051 pin-out and includes standard resources such as three
timer/counters, and 256 bytes of scratchpad RAM. This device also features 8 kbytes of EPROM with an
extra 1 kbyte of data RAM (in addition to the 256 bytes of scratchpad RAM), and 55 I/O ports pins. Both
One-Time-Programmable (OTP) and windowed packages are available.
Besides greater speed, the DS87C550 includes a second full hardware serial port, seven additional
interrupts, a programmable watchdog timer, brownout monitor, and power-fail reset.
The DS87C550 also provides dual data pointers (DPTRs) to speed block data memory moves. The usercan also dynamically adjust the speed of external accesses between two and 12 machine cycles for
flexibility in selecting memory and peripherals.
Power Management Mode (PMM) is useful for portable or battery-powered applications. This feature
allows software to select a lower speed clock as the main time base. While normal operation has a
machine cycle rate of 4 clocks per cycle, the PMM allows the processor to run at 1024 clocks per cycle.For example, at 12 MHz, standard operation has a machine cycle rate of 3 MHz. In Power Management
Mode, software can select an 11.7 kHz (12 MHz/1024) machine cycle rate. There is a corresponding
reduction in power consumption due to the processor running slower.
The DS87C550 also offers two features that can significantly reduce electromagnetic interference (EMI).
One EMI reduction feature allows software to select a reduced emission mode that disables the ALE
signal when it is unneeded. The other EMI reduction feature controls the current to the address and data
pins interfacing to external devices producing a controlled transition of these signals.
ORDERING INFORMATION
DS87C550
DS87C550 BLOCK DIAGRAM Figure 1
DS87C550
PIN DESCRIPTION Table 1
DS87C550
DS87C550
DS87C550
COMPATIBILITYThe DS87C550 is a fully static, CMOS 8051-compatible microcontroller designed for high performance.While remaining familiar to 8051 family users, it has many new features. With very few exceptions,
software written for existing 8051-based systems works without modification on the DS87C550. The
exception is critical timing since the High Speed Micro performs its instructions much faster than the
original for any given crystal selection. The DS87C550 runs the standard 8051 family instruction set andis pin-compatible with existing devices with similar features in PLCC or QFP packages.
The DS87C550 provides three 16-bit timer/counters, two full-duplex serial ports, 256 bytes of direct
RAM plus 1 kbyte of extra MOVX RAM. I/O ports have the same operation as a standard 8051 product.
Timers will default to a 12 clock per cycle operation to keep their timing compatible with original 8051
family systems. However, timers are individually programmable to run at the new 4 clocks per cycle ifdesired.
The DS87C550 provides several new hardware features implemented by new Special Function Registers.
A summary of all SFRs is provided in Table 2.
PERFORMANCE OVERVIEWThe DS87C550 features a high-speed, 8051-compatible core. Higher speed comes not just from
increasing the clock frequency, but from a newer, more efficient design.
This updated core does not have the dummy memory cycles that are present in a standard 8051. A
conventional 8051 generates machine cycles using the clock frequency divided by 12. In the DS87C550,the same machine cycle takes 4 clocks. Thus the fastest instruction, 1 machine cycle, executes three times
faster for the same crystal frequency. Note that these are identical instructions. The majority of
instructions on the DS87C550 will see the full 3 to 1 speed improvement. However, some instructions
will achieve between 1.5 and 2.4 to 1 improvement. Regardless of specific performance improvements,
all instructions are faster than the original 8051.
The numerical average of all opcodes gives approximately a 2.5 to 1 speed improvement. Improvement of
individual programs will depend on the actual mix of instructions used. Speed sensitive applications
would make the most use of instructions that are 3 times faster. However, the sheer number of 3 to 1
improved opcodes makes dramatic speed improvements likely for any arbitrary combination ofinstructions. These architecture improvements and the sub-micron CMOS design produce a peak
instruction cycle in 121 ns (8.25 MIPs). The Dual Data Pointer feature also allows the user to eliminate
wasted instructions when moving blocks of memory.
INSTRUCTION SET SUMMARYAll instructions in the DS87C550 perform exactly the same functions as their 8051 counterparts. Their
effect on bits, flags, and other status functions is identical. However, the timing of each instruction isdifferent. This applies both in absolute and relative number of clocks.
For absolute timing of real-time events, the timing of software loops can be calculated using a table in the
High Speed Micro User’s Guide. However, counter/timers default to run at the old 12 clocks perincrement. In this way, timer-based events occur at the standard intervals with software executing at
higher speed. Timers optionally can run at 4 clocks per increment to take advantage of faster processor
operation.
DS87C550
instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of
time. In the DS87C550, the MOVX instruction takes as little as two machine cycles or eight oscillator
cycles, but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While both are
faster than their original counterparts, they now have different execution times. This is because the
DS87C550 usually uses one instruction cycle for each instruction byte. Examine the timing of eachinstruction for familiarity with the changes. Note that a machine cycle now requires just 4 clocks, and
provides one ALE pulse per cycle. Many instructions require only one cycle, but some require five. In the
original architecture, all were one or two cycles except for MUL and DIV. Refer to the High Speed Micro
User’s Guide for details and individual instruction timing.
SPECIAL FUNCTION REGISTERSSpecial Function Registers (SFRs) control most special features of the DS87C550. This allows theDS87C550 to have many new features but use the same instruction set as the 8051. When writing
software to use a new feature, an equate statement defines the SFR to an assembler or compiler. This is
the only change needed to access the new function. The DS87C550 duplicates the SFRs contained in the
standard 80C52. Table 2 shows the register addresses and bit locations. Many are standard 80C52registers. The High Speed Micro User’s Guide describes all SFRs in full detail.
SPECIAL FUNCTION REGISTER LOCATION: Table 2
DS87C550
SPECIAL FUNCTION REGISTER LOCATION: Table 2 cont’d
DS87C550
MEMORY RESOURCESAs is convention within the 8051 architecture, the DS87C550 uses three memory areas. The total memoryconfiguration of the DS87C550 is 8 kbytes of EPROM, 1 kbyte of data SRAM and 256 bytes of
scratchpad or direct RAM. The 1 kbyte of data space SRAM is read/write accessible and is memory
mapped. This on-chip SRAM is reached by the MOVX instruction. It is not used for executable
memory. The scratchpad area is 256 bytes of register mapped RAM and is identical to the RAM found onthe 80C52. There is no conflict or overlap among the 256 bytes and the 1k as they use different
addressing modes and separate instructions.
OPERATIONAL CONSIDERATIONThe erasure window of the windowed CLCC package should be covered without regard to the
programmed/unprogrammed state of the EPROM. Otherwise, the device may not meet the AC and DC
parameters listed in the datasheet.
PROGRAM MEMORYOn-chip ROM begins at address 0000h and is contiguous through 1FFFh (8k). Exceeding the maximum
address of on-chip ROM will cause the DS87C550 to access off-chip memory. However, the maximum
on-chip decoded address is selectable by software using the ROMSIZE feature. Software can cause the
DS87C550 to behave like a device with less on-chip memory. This is beneficial when overlapping
external memory, such as Flash, is used.
With the ROMSIZE feature the maximum on-chip memory size is dynamically variable. Thus a portion
of on-chip memory can be removed from the memory map to access off-chip memory, then restored to
access on-chip memory. In fact, all of the on-chip memory can be removed from the memory map,allowing the full 64k memory space to be addressed as off-chip memory. ROM addresses that are larger
than the selected maximum are automatically fetched from outside the part via Ports 0 & 2. A depiction
of the ROM memory map is shown in Figure 2.
The ROMSIZE register is used to select the maximum on-chip decoded address for ROM. Bits RMS2,
RMS1, RMS0 (ROMSIZE2:0) have the following effect.
Maximum on-chip
RMS2RMS1RMS0ROM Address000k0011k (0h - 03FFh)102k (0h - 07FFh)114k (0h - 0FFFh)
008k (0h – 1FFFh) default01invalid - reserved10invalid - reserved111invalid - reserved
The reset default condition is a maximum on-chip ROM address of 8 kbytes. Thus no action is required if
this feature is not used. Therefore when accessing external program memory, the first 8 kbytes would beinaccessible. To select a smaller effective ROM size, software must alter bits RMS2-RMS0. Altering
these bits requires a Timed Access procedure as explained below. The ROMSIZE register should be
manipulated from a safe area in the program memory map. This is a program memory address that will
DS87C550
For example, do not select a maximum ROM address of 8k from an external ROM address of 7k (if
ROMSIZE is set for 4k or less).
Off-chip memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2.
While serving as a memory bus, these pins are not available as I/O ports. This convention follows thestandard 8051 method of expanding on-chip memory. Off-chip ROM access also occurs if the EA pin is
logic 0. EA overrides all bit settings. The PSEN signal will go active (low) to serve as a chip enable or
output enable when Ports 0 & 2 fetch from external ROM.
ROM MEMORY MAP Figure 2
DATA MEMORYUnlike many 8051 derivatives, the DS87C550 contains additional on-chip data memory. In addition tothe standard 256 bytes of data RAM accessed by direct instructions, the DS87C550 contains another 1
kbyte of data memory that is accessed using the MOVX instruction. Although physically on-chip,
software treats this area as though it was located off-chip. The 1 kbyte of SRAM is permanently located
from address 0000h to 03FFh (when enabled).
Access to the on-chip data RAM is optional under software control. When enabled by software, the data
SRAM is between 0000h and 03FFh. Any MOVX instruction that uses this area will go to the on-chip
RAM while enabled. MOVX addresses greater than 1k automatically go to external memory through
Ports 0 & 2.
When disabled, the 1k memory area is transparent to the system memory map. Any MOVX directed to
the space between 0000h and FFFFh goes to the expanded bus on Ports 0 & 2. This also is the default
condition. This default allows the DS87C550 to drop into an existing system that uses these addresses for
other hardware and still have full compatibility.
The on-chip data area is software selectable using two bits in the Power Management Register (DME1,
DME0). This selection is dynamically programmable. Thus access to the on-chip area becomes
transparent to reach off-chip devices at the same addresses. These bits have the following operation:
DS87C550
DATA MEMORY ACCESS CONTROL Table 3Notes on the status byte read at FFFCh with DME1, 0 = 1, 1: bits 2-0 reflect the programmed status of the
security lock bits LB2-LB0. They are individually set to a logic 1 to correspond to a security lock bit that
has been programmed. These status bits allow software to verify that the part has been locked before
running if desired. The bits are read only.
STRETCH MEMORY CYCLE
The DS87C550 allows software to adjust the speed of off-chip data memory and/or peripheral access by
adjusting the number of machine cycles it takes to execute a MOVX instruction. The micro is capable of
performing the MOVX in as little as two machine cycles. The on-chip SRAM uses this speed and any
MOVX instruction directed internally always uses two cycles. However, the time for the instructionexecution can be stretched for slower interface to external devices. This allows access to both fast
memory and slow memory or peripherals with no glue logic. Even in high-speed systems, it may not be
necessary or desirable to perform off-chip data memory access at full speed. In addition, there are a
variety of memory mapped peripherals such as LCDs or UARTs that are slow and require more time to
access.
The Stretch MOVX function is controlled by the MD2-MD0 SFR bits in the Clock Control Register
(CKCON.2-0) as described below. They allow the user to select a Stretch value between 0 and 7. A
Stretch of 0 will result in a two-machine cycle MOVX instruction. A Stretch of 7 will result in a MOVX
of 12 machine cycles. Software can dynamically change the stretch value depending on the particularmemory or peripheral being accessed. The default stretch of one allows the use of commonly available
SRAMs without dramatically lengthening the memory access times.
Note that the STRETCH MOVX function is slightly different in the DS87C550 than in earlier members
of the high-speed microcontroller family. In all members of this family (including the DS87C550),
increasing the stretch value from 0 to 1 causes setup and hold times to be increased by 1 crystal clockeach. In older members of the family, there is no further change in setup and hold times regardless of the
number of stretch cycles selected. In the DS87C550 however, when a stretch value of 4 or above is
selected, the timing of the interface changes dramatically to allow for very slow peripherals. First, the
ALE signal is increased by 1 machine cycle. This increases the address setup time into the peripheral bythis amount. Next, the address is held on the bus for one additional machine cycle, increasing the address
hold time by this amount. The Read or Write signal is then increased by a machine cycle. Finally, the data
is held on the bus (for a write cycle) one additional machine cycle, thereby increasing the data hold time
by this amount. For every Stretch value greater than 4, the setup and hold times remain constant, and only
the width of the read or write signal is increased.
DS87C550
Stretch setting. When maximum speed is desired, software should select a Stretch value of 0. When using
very slow RAM or peripherals, the application software can select a larger Stretch value. Note that this
affects data memory accesses only and that there is no way to slow the accesses to program memory other
than to use a slower crystal (or external clock).
The specific timing of the variable speed Stretch MOVX is provided in the Electrical Specifications
section of this data sheet. Table 4 shows the resulting MOVX instruction timing and the read or write
strobe widths for each Stretch value.
DATA MEMORY CYCLE STRETCH VALUES Table 4
CKCON.2-0MOVX MACHINEWR STROBE WIDTH
M1M0CYCLESIN MACHINE CYCLES002 (forced internal)0.5013 (default external)11042011530094011051011611127
Dual Data Pointer With Inc/Dec
The DS87C550 contains several new, unique features that are associated with the Data Pointer register. In
the original 8051 architecture, the DPTR was a 16-bit value that was used to address off-chip data RAM
or peripherals. To improve the efficiency of data moves, the DS87C550 contains two Data Pointerregisters (DPTR0 and DPTR1). By loading one DPTR with the source address and the other with the
destination address, block data moves can be made much more efficient. Since DPTR0 is located at the
same address as the single DPTR in the original 8051 architecture, code written for the original
architecture will operate normally on the DS87C550 with no modification necessary.
The second data pointer, DPTR1 is located at the next two register locations (up from DPTR0) and isselected using the data pointer select bit SEL (DPS.0). If SEL = 0, then DPTR0 is the active data pointer.
Conversely, if SEL = 1, then DPTR1 is the active data pointer. Any instruction that reference the DPTR
(ex. MOVX A, @ DPTR) refers to the active data pointer as determined by the SEL bit. Since the bitadjacent to SEL in the DPS register is not used, the fastest means of changing the SEL (and thereby
changing the active data pointer) is with an INC instruction. Each INC DPS Instruction will toggle the
active data pointer.
Unlike the standard 8051, the DS87C550 has the ability to decrement as well as increment the data
pointers without additional instructions. When the INC DPTR instruction is executed, the active DPTR isincremented or decremented according to the ID1, ID0 (DPS.7-6), and SEL (DPS.0) bits as shown. The
inactive DPTR is not affected.
DS87C550
Another useful feature of the device is its ability to automatically switch the active data pointer after a
DPTR-based instruction is executed. This feature can greatly reduce the software overhead associated
with data memory block moves, which toggle between the source and destination registers. When the
Toggle Select bit (TSL;DPS.5) is set to 1, the SEL bit (DPS.0) is automatically toggled every time one of
the following DPTR related instructions are executed: INC DPTR MOV DPTR, #data16 MOVC A, @A+DPTR MOVX A, @DPTR§ MOVX @DPTR, A
As a brief example, if TSL is set to 1, then both data pointers can be updated with the two instruction
series shown.
INC DPTR
INC DPTR
With TSL set, the first increment instruction increments the active data pointer, and then causes the SEL
bit to toggle making the other DPTR active. The second increment instruction increments the newlyactive data pointer and then toggles SEL to make the original data pointer active again.
CLOCK CONTROL and POWER MANAGEMENTThe DS87C550 includes a number of unique features that allow flexibility in selecting system clock
sources and operating frequencies. To support the use of inexpensive crystals while allowing full-speed
operation, a clock multiplier is included in the processor’s clock circuit. Also, along with the Idle andpower-down (Stop) modes of the standard 80C52, the DS87C550 provides a new Power Management
mode. This mode allows the processor to continue instruction execution at a very low speed to
significantly reduce power consumption (below even idle mode). The DS87C550 also features several
enhancements to Stop mode that make this extremely low power mode more useful. Each of these
features is discussed in detail below.
SYSTEM CLOCK CONTROLAs mentioned previously, the DS87C550 contains special clock control circuitry that simultaneously
provides maximum timing flexibility and maximum availability and economy in crystal selection. There
are two basic functions to this circuitry: a frequency multiplier and a clock divider. By including a
frequency multiplier circuit, full-speed operation of the processor may be achieved with a lower
frequency crystal. This allows the user the ability to choose a more cost-effective and easily obtainablecrystal than would be possible otherwise.
The logical operation of the system clock divide control function is shown in Figure 3. The clock signal
from the crystal oscillator (or external clock source) is provided to the frequency multiplier module, to a
divide-by-256 module, and to a 3-to-1 multiplexer. The output of this multiplexer is considered the
system clock. The system clock provides the time base for timers and internal peripherals, and feeds theCPU State Clock Generation circuitry. This circuitry divides the system clock by 4, and it is the four
phases of this clock that make up the instruction execution clock. The four phases of a single instruction
execution clock are also called a single machine cycle clock. Instructions in the DS87C550 all use the
DS87C550
important to remember that all timers and internal peripherals operate off of some version of the system
clock while the instruction execution engine always operates off of the machine cycle clock.
When CD1 and CD0 (PMR.7-6) are both cleared to a logic 0, the multiplexer selects the frequency
multiplier output. The frequency multiplier can supply a clock that is 2 times or 4 times the frequency of
the incoming signal. If the times-4 multiplier is selected by setting the 4X/
example, the incoming signal is multiplied by 4. This 4X clock is then passed through the multiplexer,
and then output to the CPU State Clock Generation circuits. These CPU State Clock Generation circuits
always divide the incoming clock by 4 to arrive at the four states (called a machine cycle) necessary forcorrect processor operation. In this example, since the clock multiplier multiplies by four and the CPU
State Clock Generation circuit divides by 4, the apparent instruction execution speed is 1 external (or
crystal oscillator) clock per instruction. If the 4X/
execution speed is 2 clocks per instruction.
It is important to note that the clock multiplier function does not increase the maximum clock (system
clock) rate of the device. The DS87C550 operates at a maximum system clock rate of 33 MHz. Therefore,
the maximum crystal frequency is 8.25 MHz when a clock multiplier of 4 is used, and is 16.5 MHz whena clock multiplier of 2 is used. The purpose of the clock multiplier is to simplify crystal selection when
maximum processor operation is desired. Specifically, an 8.25 MHz fundamental mode, AT cut, parallel
resonant crystal is much easier to obtain than the same crystal at 33 MHz. Most crystals in that frequency
range tend to be third overtone type.
As illustrated in Figure 3, the programmable Clock Divide control bits CD1-CD0 (PMR.7-6) provide theprocessor with the ability to adapt to different crystal (and external clock) frequencies and also to allow
extreme division of the incoming clock providing lower power operation when desired. The effect of
these bits is shown in Table 5.
CD1:CD0 OPERATION Table 5Besides the ability to use a multiplied clock signal, the normal mode of operation, i.e. the reset default
condition (CD1 = 1, CD0 = 0) passes the incoming crystal or external oscillator clock signal straight
through as the system clock. Because of the CPU State Clock generation circuitry’s normal divide-by-4
function, the default execution speed of the DS87C550’s basic instruction is one-fourth the clockfrequency.
The selection of instruction cycle rate takes effect after a delay of one machine cycle. Note that the clock
divider choice applies to all functions including timers. Since baud rates are altered, it may be difficult toconduct serial communication while in divide-by-1024 mode. This is simplified by the use of switchback
mode (described later) included on the DS87C550.
DS87C550
CLOCK SWITCHING RESTRICTIONS
To ensure clean “glitch-free” switching of the system clock and to ensure that all clocks are running andstable before they are used, there are minor restrictions on accessing the clock selection bits CD1:0 and
the 4X/
One restriction is that any change in the CD1 and CD0 bits from a condition other than a 1 0 state (i.e.,
clock divided by 4 mode) must pass through the divide-by-4 state before proceeding to the desired state.
As a specific example, if the clock divisor bits are set to use the frequency multiplier in 4X mode, no
other clock setting is possible until after the CD1:0 bits are set to divide-by-4 mode. After setting clock
divided-by-4 mode, then clock divided by 1024 can be selected by setting CD1 and CD0 to “11b”. Anyattempt to change these bits to a disallowed state will be ignored by the hardware.
There are also some minor restrictions when changing from one clock multiplier to another. Changing the
clock multiplier can only be performed when the Crystal Multiplier Enable bit CTM (PMR.4) is set to 0.
This bit disables the clock multiplication function. However, the CTM bit can only be changed when CD1and CD0 are set to divide-by-4 mode (i.e., “10b”) and the ring mode (RNGMD = RCON.2) bit is 0
(discussed later). Changing the clock multiplication factor also requires that the new frequency be stable
prior to effecting the change. The SFR bit CKRDY (RCON.3) indicates the state of the stabilization
timeout. Setting the CTM bit to a 0 from a 1 disables the clock multiplier function, automatically clears
the CKRDY bit, and starts the stabilization timeout.
SYSTEM CLOCK CONTROL Figure 3During the stabilization period, CKRDY will remain low, and software will be unable to set the CD1:0bits to select the frequency multiplier. After the stabilization delay, CKRDY will be set to a 1 by
hardware. Note that this bit cannot be set to 1 by software. After hardware sets CKRDY bit, then the
CD1:0 bits can be set to use the clock multiplier function. However, before changing CD1:0, the 4X/bit must be set to the desired state. Following this, the CTM bit must be set to 1 to enable the crystal
multiplier. Finally the CD1:0 bits may be set to select the crystal multiplier function. By following this
procedure, the processor is guaranteed to receive a stable, glitch-free clock.
OSCILLATOR-FAIL DETECTThe DS87C550 contains a unique safety mechanism called an on-chip Oscillator-Fail Detect circuit.
When enabled, this circuit causes the processor to be reset if the oscillator frequency falls below TBDkHz. The processor is held in reset until the oscillator frequency rises above TBD kHz. In operation, this
circuit can provide a backup for the watchdog timer. Normally, the watchdog timer is initialized so that it
will timeout and will cause a processor reset in the event that the processor loses control. This works
perfectly as long as there is a clock from the crystal or external oscillator, but if this clock fails, there is
DS87C550
The oscillator-fail detect circuitry is enabled by software setting the enable bit OFDE (PCON.4) to a 1.
Please note that software must use a “Timed Access” procedure (described later) to write to this bit. There
is an oscillator-fail detect flag, OFDF (PCON.5), that is set to a 1 by the hardware when it detects an
oscillator failure. The processor will be forced into a reset state when this occurs if enabled by OFDE.
The oscillator-fail detect flag can only be cleared to a 0 by a power-up reset or by software. It should benoted that the oscillator-fail detect circuitry is not disabled by entering Stop mode. There fore, the user
must ensure that this feature is disabled before entering Stop mode.
POWER MANAGEMENT MODE (PMM)Power Management Mode offers a complete scheme of reduced internal clock speeds that allow the CPU
to run software but to use substantially less power. Normally, during default operation, the DS87C550
uses 4 clocks per machine cycle. Thus the instruction cycle (machine cycle clock) rate is Clock/4. At 33MHz crystal speed, the instruction cycle speed is 8.25 MHz. In PMM the microcontroller operates, but
from an internally divided version of the clock source. This creates a lower power state without external
components. As shown in Figure 3, the system clock may be selected to use the crystal (or external
oscillator) frequency divided by 256. This produces a machine cycle that consists of the crystal frequencydivided by 1024, which is considered Power Management Mode (PMM). With the processor executing
instructions at this much lower rate, a significant amount of power is saved.
Software is the only mechanism to invoke the PMM. Table 6 illustrates the instruction cycle rate in
PMM for several common crystal frequencies. Since power consumption is a direct function of operating
speed, PMM runs very slowly and provides the lowest power consumption without stopping the CPU.This is illustrated in Table 7.
MACHINE CYCLE RATE Table 6
Full OperationPMM
Crystal Speed(4 clocks per machine cycle)(1024 clocks per machine cycle)11.0592 MHz2.765 MHz10.8 kHz
16 MHz4.0 MHz15.6 kHz
25 MHz6.25 MHz24.4 kHz
33 Mhz8.25 MHz32.2 kHz
OPERATING CURRENT ESTIMATES IN PMM Table 7
Full OperationPMM
Crystal Speed(4 clocks per machine cycle)(1024 clocks per machine cycle)11.0592 MHz13.1 mA4.8 mA
16 MHz17.2 mA5.6 mA
25 MHz25.7 mA7.0 mA
33 Mhz32.8 mA8.2 mA
DS87C550
faster than wakeup from Idle, and since PMM allows the CPU to continue to execute instructions (even if
doing NOPs), there is little reason to use Idle in new designs.
SwitchbackOne of the other unique features included on the DS87C550 is Switchback. Simply, Switchback when
enabled will allow serial ports and interrupts to automatically switch back from divide-by-1024 (PMM) todivide-by-4 (standard speed operation). This feature makes it very convenient to use the Power
Management Mode in real time applications. Of course to return to a divide-by-4 clock rate from divide-
by-1024 PMM, software can simply select the CD1 & CD0 clock control bits to the 4 clocks per cycle
state. However, the DS87C550 provides hardware alternatives for automatic Switchback to standard
speed operation.
The Switchback feature is enabled by setting the SFR bit SWB (PMR.5) to a 1. Once it is enabled and
when PMM is selected, there are two possible events that can cause an automatic switchback to divide-
by-4 mode. First, if an interrupt occurs and is set so that it will be acknowledged, this event will cause
the system clock to revert from PMM to divide-by-4 mode. For example, if INT0 is enabled then
Switchback will occur on INT0. However, if INT0 is not enabled, then activity on INT0 will not cause
switchback to occur.
A Switchback can also occur when an enabled UART detects the start bit indicating the beginning of an
incoming serial character or when the SBUF register is loaded initiating a serial transmission. Note that a
serial character’s start bit does not generate an interrupt. This occurs only on reception of a complete
serial word. The automatic Switchback on detection of a start bit allows hardware to correct baud rates in
time for a proper serial reception or transmission. So with Switchback enabled and a serial port enabled,the automatic switch to normal speed operation occurs automatically in time to receive or transmit a
complete serial character as if nothing special had happened.
Once Switchback causes the processor to make the transition back to divide-by-4 mode, software mustmodify SFR bits CD1 & CD0 to re-enter Power Management Mode. However, if a serial port is in the
process of transmitting or receiving a character, then this change back to PMM will not be allowed as the
hardware prevents a write to CD1 & CD0 during any serial port activity.
Since the reception of a serial start bit or an interrupt priority lockout is normally undetectable by
software in an 8051, the Status register features several new flags that are useful. These are describedbelow.
StatusInformation in the Status register assists decisions about switching into PMM. This register contains
information about the level of active interrupts and the activity on the serial ports.
The DS87C550 supports three levels of interrupt priority. These levels are Power-fail, High, and Low.
Status bits STAT.7-5 indicate the service status of each level. If PIP (Power-fail Interrupt Priority;
STATUS.7) is a 1, then the processor is servicing this level. If either HIP (High Interrupt Priority;
STATUS.6) or LIP (Low Interrupt Priority; STATUS.5) is high, then the corresponding level is in
service.
Software should not rely on a lower priority level interrupt source to remove PMM (Switchback) when a
DS87C550
Alternately, software can prevent an undesired exit from PMM by entering a low priority interrupt service
level before entering PMM. This will prevent other low priority interrupts from causing a Switchback.
Status also contains information about the state of the serial ports. Serial Port Zero Receive Activity(SPRA0; STATUS.0) indicates a serial word is being received on Serial Port 0 when this bit is set to a 1.
Serial Port Zero Transmit Activity (SPTA0; STATUS.1) indicates that the serial port is still shifting out a
serial transmission. STATUS.2 (SPRA1) and STATUS.3 (SPTA1) provide the same information for
Serial Port 1, respectively. While one of these bits is set, hardware prohibits software from entering PMM
(CD1 & CD0 are write-protected) since this would corrupt the corresponding serial transmissions.
IDLE MODESetting the LSB of the Power Control register (PCON.0) invokes the Idle mode. Idle will leave internal
clocks, serial ports and timers running. Power consumption drops because memory is not being accessed
and instructions are not being executed. Since clocks are running, the Idle power consumption is a
function of crystal frequency. It should be approximately ½ of the operational power at a givenfrequency. The CPU can exit the Idle state with any interrupt or a reset. Idle is available for backward
software compatibility. However, due to improvements over the original architecture, the processor’s
power consumption can be reduced to below Idle levels by invoking Power Management Mode (PMM)
and running NOPs.
STOP MODESetting bit 1 of the Power Control register (PCON.1) invokes the Stop mode. Stop mode is the lowestpower state (besides power-off) since it turns off all internal clocking. The ICC of a standard Stop mode isapproximately 1 uA (but is specified in the Electrical Specifications). All processor operation ceases at
the end of the instruction that sets PCON.1. The CPU can exit Stop mode from an external interrupt or a
reset condition. Internally generated interrupts (timer, serial port, etc.) are not useful since they require
clocking activity.
BAND-GAP SELECT
The DS87C550 provides two enhancements to the Stop mode. As described below, the DS87C550
provides a band-gap reference to determine Power-fail Interrupt and Reset thresholds. The default state is
that the band-gap reference is off while in Stop mode. This mode allows the extremely low-power state
mentioned above. A user can optionally choose to have the band-gap enabled during Stop mode. With theband-gap reference enabled, PFI and Power-fail Reset are functional and are valid means for leaving Stop
mode. This allows software to detect and compensate for a brownout or power supply sag, even when in
Stop mode.
In Stop mode with the band-gap enabled, ICC will be approximately 100 uA compared with 1 uA with the
band-gap off. If a user does not require a Power-fail Reset or Interrupt while in Stop mode, the band-gapcan remain disabled. Only the most power-sensitive applications should turn off the band-gap, as this
results in an uncontrolled power-down condition.
The control of the band-gap reference is located in the Ring Oscillator Control Register (RCON). SettingBGS (RCON.0) to a 1 will keep the band-gap reference enabled during Stop mode. The default or reset
condition is with the bit at a logic 0. This results in the band-gap being off during Stop mode. Note that
this bit has no control of the reference during full power, PMM, or Idle modes.
DS87C550
RING OSCILLATOR
The second enhancement to Stop mode on the DS87C550 allows an additional power saving option whilealso making Stop easier to use. This is the ability to start instantly when exiting Stop mode. It is the
internal ring oscillator that provides this feature. This ring can be a clock source when exiting Stop mode
in response to an interrupt. The benefit of the ring oscillator is as follows.
Entering Stop mode turns off the crystal oscillator and all internal clocks to save power. When exiting
Stop mode, the external crystal may require up to 10 ms to begin oscillating again. The DS87C550 can
eliminate that delay through the use of the internal ring oscillator, resuming operation in less than 100 ns
when exiting Stop mode. If a user selects the ring to provide the start-up clock and the processor remains
running, hardware will automatically switch to the crystal once a power-on reset interval (65536 crystal
clocks) has expired.
The ring oscillator runs at approximately 4 MHz but will not be a precise value. Do not conduct real-time
precision operations (including serial communication) during this ring period. The default state is to exit
Stop mode without using the ring oscillator, so action to enable the ring must be taken before enteringstop mode.
The Ring Select (RGSL) bit in the RCON register (RCON.1) controls this function. When RGSL = 1, the
CPU will use the ring oscillator to exit Stop mode quickly. As mentioned above, the processor will
automatically switch from the ring to the crystal after a delay of 65,536 crystal clocks. For a 3.57 MHz
crystal, this is approximately 18 ms. The processor sets a flag called Ring Mode (RGMD = RCON.2) thattells software that the ring is being used. The bit will be a logic 1 when the ring is in use.
TIMED ACCESS PROTECTIONSelected SFR bits are critical to operation, making it desirable to protect them against an accidental write
operation. The Timed Access procedure prevents an errant processor from accidentally altering a bit that
would seriously affect processor operation. The Timed Access procedure requires that the write of aprotected bit be preceded by the following instructions:
MOV 0C7h, #0AAh
MOV 0C7h, #55h
By writing an AAh followed by a 55h to the Timed Access register (location C7h), the hardware opens a
three-cycle window that allows software to modify one of the protected bits. If the instruction that seeks
to modify the protected bit is not immediately preceded by these instructions, the write will not take
effect. The protected bits are:
WDCON.6PORPower-On Reset Flag
WDCON.3WDIFWatchdog Interrupt Flag
WDCON.1EWTWatchdog Reset Enable
WDCON.0RWTReset Watchdog Timer
RCON.0BGSBand-Gap Select
DS87C550
ROMSIZE.1RMS1Program Memory Select
Bit 1
ROMSIZE.0RMS0Program Memory SelectBit 0
EMI REDUCTIONOne of the major contributors to radiated noise in an 8051-based system is the toggling of ALE. The
DS87C550 allows software to disable ALE when not used by setting the ALEOFF (PMR.2) bit to a 1.
When ALEOFF = 1, ALE will still toggle during an off-chip MOVX. However, ALE will remain inactive
when performing on-chip memory access. The default state is ALEOFF = 0 so ALE normally toggles at afrequency of XTAL/4.
PERIPHERAL OVERVIEWThe DS87C550 provides several of the most commonly needed peripheral functions in microcomputer-
based systems. New functions include a second serial port, power-fail reset, power-fail interrupt flag, and
a programmable watchdog timer. In addition, the DS87C550 contains an analog-to-digital converter andfour channels of pulse width modulation for industrial control and measurement applications. Each of
these peripherals is described below. More details are available in the High-Speed Micro Data Book (or
its most recent addendum).
SERIAL PORTSThe DS87C550 provides a serial port (UART) that is identical to the 80C52. In addition, it includes asecond hardware serial port that is a full duplicate of the standard one. This port optionally uses pins P1.6
(RXD1) and P1.7 (TXD1). It has duplicate control functions included in new SFR locations.
Both ports can operate simultaneously but can be at different baud rates or even in different modes. The
second serial port has similar control registers (SCON1, SBUF1) to the original. The new serial port can
only use Timer 1 for timer generated baud rates.
Control for serial port 0 is provided by the SCON0 register while its I/O buffer is SBUF0. The registers
SCON1 and SBUF1 provide the same functions for the second serial port. A full description of the use
and operation of both serial ports may be found in the “High-Speed Microcontroller Data Book.”
ANALOG TO DIGITAL CONVERTERThe DS87C550 contains a 10-bit successive approximation analog-to-digital converter. This converter
provides eight multiplexed channels of analog input and allows the user to select either an external or
internal precision voltage reference to be used for the conversion process. The A/D converter provides
true 9-bit accuracy with a total error of less than ±2 LSBs.
The A/D Converter may be disabled to conserve power by writing a 0 to the SFR ADON bit
(ADCON1.1). At reset, this is the default condition, and the user must write a 1 to this bit prior to using
the A/D Converter.
A/D CONVERTER INPUT
The A/D Converter of the DS87C550 provides eight channels of analog input on device pins ADC7
DS87C550
Specifications section). This reference voltage may be selected to be either an internal band-gap voltage
(VBG) or an external reference (Avref+, Avref-). This selection is made by writing a 0 (uses internal
reference VBG) or writing a 1 (uses external reference (Avref+, Avref-) to the ADRS bit (PWMADR.7).
The default reset condition is for the internal reference to be selected.
Selecting a single analog signal for conversion is achieved by software writing the desired channel
number (0 through 7) into SFR bits MUX2 through MUX0 bits of the A/D Control Register 2
(ADCON2.6-4). The single output of the multiplexer is then provided to a sample and hold circuit that
maintains a steady signal during the conversion process.
A/D CONVERSION PROCESS
The A/D conversion process can be configured for one-shot or continuous mode operation. For one-shotoperation, the SFR bit CONT/SS (ADCON1.5) must be a 0. The conversion process is then initiated by
software writing a 1 to the STRT/BSY SFR bit (ADCON1.7) if the ADEX (ADCON1.4) bit is a 0. If the
ADEX bit is a 1, then the conversion is initiated by an active low signal on the external pin STADC
(P6.7). If continuous mode is selected (CONT/SS = 1), then the first conversion is initiated as describedabove, but another conversion will be automatically started at the completion of the previous conversion.
Once initiated, the conversion process requires 16 A/D clock periods (TACLK) to complete. Because of thedynamic nature of the converter, the A/D clock period can be no less that 1 us and no more than 6.25 us.
This requirement is expressed as follows:
1.0 us <= TACLK <= 6.25 us
Therefore any single conversion time can range from 16 us minimum to 100 us maximum, depending on
the selected A/D clock frequency.
The A/D clock frequency is a function of the processor’s machine cycle clock and the A/D clock’s
prescaler setting as shown by the following equation:
TACLK = TMCLK * (N+1)
where N is the prescaler setting in APS3:0.
The processor’s machine cycle clock period (TMCLK) is normally the external crystal (or oscillator)
frequency multiplied by 4 (but can be affected by the CD1, CD0, and 4X/
must be set by the user to ensure that it falls within the minimum and maximum values specified above.
As an example, assume the processor’s crystal frequency is 33 MHz and that the processor is running in a
standard divide-by-4 mode. This means that the period of the processors machine cycle clock, i.e.,
TMCLK, will be (1/33 MHz)*4 or 121.2 ns. If it is assumed that the application requires the fastest possible
conversion time, then the desired TACLK is 1.0 us. The necessary prescale value can then be calculated as:
N = (TACLK/TMCLK)-1
Therefore for this example, N = 7.25. Since N must be an integer, the value of N must be 8 (rounded upto the next integer). This results in a conversion clock TACLK = 1.091 us.
DS87C550
A/D OUTPUT
There are two SFR locations that contain the result of the A/D conversion process. They are ADMSB(most significant byte) and ADLSB (least significant byte). The ADLSB byte always contains the 8 least
significant bits of the 10-bit result. The ADMSB can be configured in two different ways through the use
of the SFR bit OUTCF (ADCON2.7). If OUTCF is a 0, then ADMSB contains the 8 most significant bits
of the 10-bit conversion (i.e., bits 9-2). If OUTCF is a 1, then ADMSB contains A/D output bits 9-8 (rightjustified). The upper 6 bits of the register are set to 0 in this case.
The value stored in the output registers is given by the following equation:
1024 x ((Vin-Avref-)/(Avref+ - Avref-))
This equation shows that the A/D conversion result is a 10-bit binary number that represents what fraction
of the available reference voltage the input signal is. As you can see with a reference voltage of 2.5 volts,
the output has a resolution of 2.44 millivolts. This shows that the reference voltage must be very well
regulated to ensure satisfactory performance. It should be noted that the output of the A/D conversionprocess will be “0000000000” for voltages from Avref- to (Avref- +1/2 LSB). In addition, “1111111111”
will be output for voltages from (Avref+ - 3/2 LSB) to Avref+.
The DS87C550 offers a unique feature that allows the result of an A/D conversion to be compared with
two user-defined values stored in the WINHI and WINLO registers. The results of this comparison will
set or clear the WCM (ADCON 1.2) bit, and this bit can be used as a qualifier to the A/D interrupt. Thiscomparison is built into hardware so that this feature is performed without any burden on the software,
and A/D results that are not of particular interest to the application can be ignored. Special function
registers WINHI and WINLO are loaded by application software with 8-bit numbers that are compared
with the 8 MSBs of the A/D result. These user-defined numbers form a range of values, and the A/Dresult is evaluated to be inside or outside of this range. When WCIO (ADCON.1) is 0, then WCM is set if
the A/D result is found to be inside the range. Otherwise WCM is cleared. When WCIO is a 1, then
WCM is set if the A/D result is found to be outside the range. Otherwise WCM is cleared. The state of the
WCM bit is expressed by the following equation:
WCM = WCIO Å (WINHI £ ADMSB) Å (WINLO £ ADMSB)
This equation precisely identifies the relationship between the window registers (WINHI and WINLO),
the MSB of the A/D conversion (ADMSB), and the WCIO and WCM bits. However by observation, it isnot particularly intuitive as to how this interaction works in a practical sense. If the user makes the
assumption that the value stored in WINHI is greater that the value stored in WINLO (this is normally but
not necessarily the case), then this equation can be simplified to the following two cases:
For WCIO = 0: WCM = (WINHI > ADMSB) AND (ADMSB ³ WINLO)
For WCIO = 1: WCM = (WINHI £ ADMSB) OR (ADMSB < WINLO)
It is clear that these two equations now express the cases where the A/D result is inside the comparison
window (WCIO = 0) and outside the comparison window (WCIO = 1). It is important to note the £ and
³ symbols and account for the specific values that are included in the comparison.
DS87C550
1, then an A/D Interrupt will only occur if WCM is set (i.e., the A/D result comparison was true). This
feature allows software to respond only to conditions that meet the programmed range.
PULSE WIDTH MODULATIONThe DS87C550 contains four independent 8-bit pulse width modulator (PWMs) functions each with
independently selectable clock sources. For more precise modulation operations, two 8-bit PWMfunctions (PWM0 & PWM1 and/or PWM2 & PWM3) can be cascaded together to form a 16-bit PWM
function.
The PWM function is divided into three major blocks: a clock prescaler, a clock generator, and a pulse
generator. A single prescaler provides selectable clocks of different frequencies to each of the four clock
generator blocks. Each clock generator is an 8-bit reloadable counter that determines the repetition rate(frequency) of its associated PWM. Each pulse generator PWM block is an 8-bit timer clocked by the
clock generator’s output. When this timer reaches zero, the output of the PWM is set to 1. When the timer
reaches the user selected PWM match value stored in SFR PWMx, the PWM output is cleared to 0. In
this way, the frequency and duty cycle of the PWM is varied under software control.
PWM PRESCALER
The prescaler block of the PWM function accepts as a clock input the system clock provided to the CPU
(and other peripherals), and divides it by 1, 4, 16, and 64. Each of these clocks is available at the output
of the prescaler, and is provided to all four of the PWM clock generator blocks. The actual clock used by
the clock generator block is dependant on the setting of SFR bits PWxS2:0 (where x is the PWM channel
number 0-3) located in the PW01CS or PW23CS registers. In addition to selecting one of the prescaler’sCPU clock divided outputs, setting PWxS2 to a 1 allows an external clock to be used as an input to the
clock generators. The external clocks are input on device pins PWMC0 (P6.4 for PWM0 or PWM1) or
PWMC1 (P6.5 for PWM2 or PWM3). Like all other inputs to the 8051, these inputs are synchronized by
sampling them using the internal machine cycle clock. Therefore these inputs must be of sufficient
duration for the clock to sample them properly (i.e., 2 machine cycles). The complete functionality of theclock selection SFR bits is as follows:
Prescaler OutputPWxS2:0Machine Cycle_Clock/1000
Machine Cycle_Clock/4001
Machine Cycle_Clock/16010
Machine Cycle_Clock/64011
PWMCx (external)1xx
In determining the exact frequency output of the prescaler, it is important to note that the machine cycleclock provided to the prescaler is also software-selectable. The machine cycle clock can be the crystal (or
oscillator frequency) divided by 1, 2, 4, or 1024 as determined by the CD1:0 and the 4X/
Clock Divide Control section for details).
DS87C550
output of the prescaler to be passed directly to the pulse generator function (i.e., divide by 1). A value of
FFh passes a clock to the pulse generator function that is the selected prescaler output divided by 256. In
general, the clock generators provide a divide by N+1 selectable repetition rate (i.e., frequency) for their
PWM channel.
Each clock generator has an associated SFR that contains the 8-bit reload value. These registers are called
PW0FG, PW1FG, PW2FG, and PW3FG (see SFR map for addresses). In addition, there is a frequency
generator enable bit (PW0EN, PW1EN, PW2EN, & PW3EN) for each of the clock generator blocks that
must be set to a 1 before these blocks will function. These bits are set to 0 after all resets so software must
set them to 1 to enable the PWM clocks.
The output of the clock generator block is supplied to the input of the pulse generator block.
PWM PULSE GENERATOR
The pulse generator block of the PWM function produces the PWM output signal on device pins
PWMO0 (P6.0), PWMO1(P6.1), PWMO2 (P6.2), AND PWMO3 (P6.3). Each of these output bits has anenable bit: PW0OE (PW01CON.5), PW1OE (PW01CON.1), PW2OE (PW23CON.5), and PW3OE
(PW23CON.1) that are cleared to 0 on all resets, and must be set to 1 by software before the PWMs will
output a signal.
As described earlier, the pulse generator block is basically a free-running timer with a comparison register
that is loaded with an 8-bit value by software. The value of this register establishes the duty cycle of thePWM function. The comparison values are stored in SFRs PWM0, PWM1, PWM2, and PWM3 for the
respective PWM channels, and it is these values that determine the pulse duration.
Actually, in accessing these specific SFRs, software has access to both the compare registers and thetimer registers of the pulse generator blocks. When the PWM Timer/Compare Value Select SFR bits
PW0T/C (PW01CON.4), PW1T/C (PW01CON.0), PW2T/C (PW23CON.4), and PW3T/C
(PW23CON.0) are cleared to 0, a read or write to the respective PWMx register accesses the compare
register. When these bits are set to 1, a read or write accesses the timer value. With the use of these bits,
the timers in the pulse generator sections of the PWM functions can be used as general purpose timers if
desired.
When the free-running timer of the pulse generator block rolls over from FFh to 00h, the PWM’s output
is set to a 1. As the timer continues to count up from 0, the output of the PWM is cleared to 0 when the
timer value is equal to the comparison register value. This cycle continues automatically withoutprocessor intervention until software or a reset changes some condition.
The value of 0 in the comparison register is a special case of each PWM function. Rather than allow a set
and a reset of the PWM output bit, special hardware ensures that 0 will be output continuously if 0 is
loaded into the compare register.
There are other SFR bits that affect PWM operation for special modes. Bits PW0DC (PW01CON.6),
PW1DC (PW01CON.2), PW2DC (PW23CON.6), and PW3DC (PW23CON.2) cause the output of the
respective PWM function to be a constant 1. This feature may be useful for driving a fixed DC voltage
into any circuitry attached to the PWM output. Bits PW0F (PW01CON.7), PW1F (PW01CON.3), PW2F(PW23CON.7), and PW3F (PW23CON.3) are flags that are set by the hardware when the respective
PWM pulse generator timer rolls over from FFh to 0. These flags must be cleared by software to remove
