DS87C530 ,EPROM Microcontrollers with Real-Time ClockFeatures Selects Effective On-Chip ROM Size from DALLAS 0 to 16kB DS87C530 Allows Access to En ..
DS87C530-ENL ,EPROM MICRO WITH REAL TIME CLOCKapplications. It also provides sev- sor slows.eral peripherals found on other Dallas High–SpeedMicr ..
DS87C530-KCL ,EPROM MICRO WITH REAL TIME CLOCKFEATURES PACKAGE OUTLINE7 147• 80C52 Compatible– 8051 Instruction set8 46– Four 8–bit I/O ports– Th ..
DS87C530QCL ,33 MHz, EPROM/ROM microcontroller with real-time clockapplications. They also provide several peripherals found on other Dallas high-speed microcontrolle ..
DS87C530-QCL ,EPROM/ROM Microcontrollers with Real-Time ClockBLOCK DIAGRAM Figure 1RTCX1 RTCX2 GND VV CC2BATVCC BATTERY REAL TIMECONTROL CLOCK1K X 8ACCUMULATOR ..
DS87C530QCL. ,33 MHz, EPROM/ROM microcontroller with real-time clockFeatures Selects Effective On-Chip ROM Size from DALLAS 0 to 16kB DS87C530 Allows Access to En ..
ECH8649 ,N-Channel Power MOSFET, 20V, 7.5A, 17mOhm, Dual ECH8Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage V 20 VDSS ..
ECH8653 ,N-Channel Power MOSFET, 20V, 7.5A, 20mOhm, Dual ECH8Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage V 20 VDSS ..
ECH8657 ,N-Channel Power MOSFET, 35V, 4.5A, 59mOhm, Dual ECH8Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage V 35 VDSS ..
DS87C530
EPROM Microcontrollers with Real-Time Clock
FEATURES
80C52 Compatible 8051 Instruction-Set Compatible
Four 8-Bit I/O Ports
Three 16-Bit Timer/Counters
256 Bytes Scratchpad RAM
Large On-Chip Memory 16kB EPROM (OTP)
1kB Extra On-Chip SRAM for MOVX
ROMSIZE Features Selects Effective On-Chip ROM Size from
0 to 16kB
Allows Access to Entire External Memory Map
Dynamically Adjustable by Software
Useful as Boot Block for External Flash
Nonvolatile Functions On-Chip Real-Time Clock with Alarm Interrupt
Battery Backup Support of 1kB SRAM
High-Speed Architecture 4 Clocks/Machine Cycle (8051 = 12)
Runs DC to 33MHz Clock Rates
Single-Cycle Instruction in 121ns
Dual Data Pointer
Optional Variable Length MOVX to Access
Fast/Slow RAM /Peripherals
Power Management Mode Programmable Clock Source Saves Power
Runs from (crystal/64) or (crystal/1024)
Provides Automatic Hardware and Software Exit
EMI Reduction Mode Disables ALE
Two Full-Duplex Hardware Serial Ports
High Integration Controller Includes: Power-Fail Reset
Early-Warning Power-Fail Interrupt
Programmable Watchdog Timer
14 Total Interrupt Sources with Six External
PIN CONFIGURATIONS
DALLAS
DS87C530
DS83C530 7 1 47 33
PLCC, WINDOWED CLCC
DALLAS
DS87C530
DS83C530 27
1 13 4052
TQFP TOP VIEW
DS87C530/DS83C530
EPROM/ROM Microcontrollers with
Real-Time ClockThe High-Speed Microcontroller User’s Guide must
be used in conjunction with this data sheet. Download it
at: /microcontrollers.
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
ORDERING INFORMATION
PART TEMP RANGE
MAX CLOCK
SPEED
(MHz)
PIN-PACKAGE
DS87C530-QCL 0C to +70C 33 52 PLCC
DS87C530-QCL+ 0C to +70C 33 52 PLCC
DS87C530-QNL -40C to +85C 33 52 PLCC
DS87C530-QNL+ -40C to +85C 33 52 PLCC
DS87C530-KCL* 0C to +70C 33 52 Windowed CLCC
DS87C530-ECL 0C to +70C 33 52 TQFP
DS87C530-ECL+ 0C to +70C 33 52 TQFP
DS87C530-ENL -40C to +85C 33 52 TQFP
DS87C530-ENL+ -40C to +85C 33 52 TQFP
DS83C530-QCL 0C to +70C 33 52 PLCC
DS83C530-QCL+ 0C to +70C 33 52 PLCC
DS83C530-QNL -40C to +85C 33 52 PLCC
DS83C530-QNL+ -40C to +85C 33 52 PLCC
DS83C530-ECL 0C to +70C 33 52 TQFP
DS83C530-ECL+ 0C to +70C 33 52 TQFP
DS83C530-ENL -40C to +85C 33 52 TQFP
DS83C530-ENL+ -40C to +85C 33 52 TQFP
+ Denotes a lead(Pb)-free/RoHS-compliant device.
* The windowed ceramic LCC package is intrinsically lead(Pb) free.
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
DETAILED DESCRIPTION The DS87C530/DS83C530 EPROM/ROM microcontrollers with a real-time clock (RTC) are 8051-
compatible microcontrollers based on the Dallas Semiconductor high-speed core. They use 4 clocks per
instruction cycle instead of the 12 used by the standard 8051. They also provide a unique mix of
peripherals not widely available on other processors. They include an on-chip RTC and battery backup
support for an on-chip 1k x 8 SRAM. The new Power Management Mode allows software to select
reduced power operation while still processing.
A combination of high-performance microcontroller core, RTC, battery-backed SRAM, and power
management makes the DS87C530/DS83C530 ideal for instruments and portable applications. They also
provide several peripherals found on other Dallas high-speed microcontrollers. These include two
independent serial ports, two data pointers, on-chip power monitor with brownout detection and a
watchdog timer.
Power Management Mode (PMM) allows software to select a slower CPU clock. While default operation
uses four clocks per machine cycle, the PMM runs the processor at 64 or 1024 clocks per cycle. There is a
corresponding drop in power consumption when the processor slows.
The EMI reduction feature allows software to select a reduced emission mode. This disables the ALE
signal when it is unneeded.
The DS83C530 is a factory mask ROM version of the DS87C530 designed for high-volume, cost-
sensitive applications. It is identical in all respects to the DS87C530, except that the 16kB of EPROM is
replaced by a user-supplied application program. All references to features of the DS87C530 will apply to
the DS83C530, with the exception of EPROM-specific features where noted. Please contact your local
Dallas Semiconductor sales representative for ordering information.
Note: The DS87C530/DS83C530 are monolithic devices. A user must supply an external battery or super cap and a 32.768kHz timekeeping crystal to have permanently powered timekeeping or nonvolatile RAM.
The DS87C530/DS83C530 provide all the support and switching circuitry needed to manage these
resources.
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
Figure 1. Block Diagram
PIN DESCRIPTION
PIN
PLCC TQFP NAME FUNCTION 52 45 VCC
+5V Processor Power Supply 1, 25 18, 46 GND
Processor Digital Circuit Ground 29 22 VCC2
+5V RTC Supply. VCC2 is isolated from VCC to isolate the RTC from digital noise. 26 19 GND2
RTC Circuit Ground 12 5 RST
Reset Input. This pin contains a Schmitt voltage input to recognize external active high reset inputs. The pin also employs an internal pulldown resistor to allow for a
combination of wired OR external reset sources. An RC is not required for power-up,
as the device provides this function internally.
23 16 XTAL2
24 17 XTAL1
Crystal Oscillator Pins. XTAL1 and XTAL2 provide support for parallel-resonant, AT-cut crystals. XTAL1 acts also as an input if there is an external clock source in
place of a crystal. XTAL2 is the output of the crystal amplifier.
DS87C530/
DS83C530
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
PIN DESCRIPTION (continued)
PIN
PLCC TQFP NAME FUNCTION 38 31 PSEN
Program Store-Enable Output. This active-low signal is a chip enable for optional external ROM memory. PSEN provides an active-low pulse and is driven high when
external ROM is not being accessed.
39 32 ALE
Address Latch-Enable Output. This pin latches the external address LSB from the multiplexed address/data bus on Port 0. This signal is commonly connected to the
latch enable of an external 373 family transparent latch. ALE has a pulse width of
1.5 XTAL1 cycles and a period of four XTAL1 cycles. ALE is forced high when the
device is in a Reset condition. ALE can be disabled and forced high by writing
ALEOFF = 1 (PMR.2). ALE operates independently of ALEOFF during external
memory accesses.
50 43 P0.0 (AD0)
49 42 P0.1 (AD1)
48 41 P0.2 (AD2)
47 40 P0.3 (AD3)
46 39 P0.4 (AD4)
45 38 P0.5 (AD5)
44 37 P0.6 (AD6)
43 36 P0.7 (AD7)
Port 0 (AD0–AD7), I/O. Port 0 is an open-drain, 8-bit, bidirectional I/O port. As an alternate function Port 0 can function as the multiplexed address/data bus to access
off-chip memory. During the time when ALE is high, the LSB of a memory address
is presented. When ALE falls to a logic 0, the port transitions to a bidirectional data
bus. This bus is used to read external ROM and read/ write external RAM memory
or peripherals. When used as a memory bus, the port provides active high drivers.
The reset condition of Port 0 is tri-state. Pullup resistors are required when using
Port 0 as an I/O port.
3 48 P1.0
4 49 P1.1
5 50 P1.2
6 51 P1.3
7 52 P1.4
8 1 P1.5
9 2 P1.6
10 3 P1.7
Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port and an alternate functional interface for Timer 2 I/O, new External Interrupts, and new Serial Port 1.
The reset condition of Port 1 is with all bits at a logic 1. In this state, a weak pullup
holds the port high. This condition also serves as an input mode, since any external
circuit that writes to the port will overcome the weak pullup. When software writes a
0 to any port pin, the device will activate a strong pulldown that remains on until
either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will
cause a strong transition driver to turn on, followed by a weaker sustaining pullup.
Once the momentary strong driver turns off, the port again becomes the output high
(and input) state. The alternate modes of Port 1 are outlined as follows.
Port Alternate Function P1.0 T2 External I/O for Timer/Counter 2
P1.1 T2EX Timer/Counter 2 Capture/Reload Trigger
P1.2 RXD1 Serial Port 1 Input
P1.3 TXD1 Serial Port 1 Output
P1.4 INT2 External Interrupt 2 (Positive Edge Detect)
P1.5 INT3 External Interrupt 3 (Negative Edge Detect)
P1.6 INT4 External Interrupt 4 (Positive Edge Detect)
P1.7 INT5 External Interrupt 5 (Negative Edge Detect)
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
PIN DESCRIPTION (continued)
PIN
PLCC TQFP NAME FUNCTION 30 23 P2.0 (AD8)
31 24 P2.1 (AD9)
32 25 P2.2 (AD10)
33 26 P2.3 (AD11)
34 27 P2.4 (AD12)
35 28 P2.5 (AD13)
36 29 P2.6 (AD14)
37 30 P2.7 (AD15)
Port 2 (A8–A15), I/O. Port 2 is a bidirectional I/O port. The reset condition of Port 2 is logic high. In this state, a weak pullup holds the port high. This condition
also serves as an input mode, since any external circuit that writes to the port will
overcome the weak pullup. When software writes a 0 to any port pin, the device
will activate a strong pulldown that remains on until either a 1 is written or a reset
occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver
to turn on, followed by a weaker sustaining pullup. Once the momentary strong
driver turns off, the port again becomes both the output high and input state. As an
alternate function Port 2 can function as MSB of the external address bus. This
bus can be used to read external ROM and read/write external RAM memory or
peripherals.
15 8 P3.0
16 9 P3.1
17 10 P3.2
18 11 P3.3
19 12 P3.4
20 13 P3.5
21 14 P3.6
22 15 P3.7
Port 3, I/O. Port 3 functions as both an 8-bit, bi-directional I/O port and an alternate functional interface for external interrupts, Serial Port 0, Timer 0 and 1
Inputs, and RD and WR strobes. The reset condition of Port 3 is with all bits at a
logic 1. In this state, a weak pullup holds the port high. This condition also serves
as an input mode, since any external circuit that writes to the port will overcome
the weak pullup. When software writes a 0 to any port pin, the device will activate
a strong pulldown that remains on until either a 1 is written or a reset occurs.
Writing a 1 after the port has been at 0 will cause a strong transition driver to turn
on, followed by a weaker sustaining pullup. Once the momentary strong driver
turns off, the port again becomes both the output high and input state. The
alternate modes of Port 3 are outlined below.
Port Alternate Function P3.0 RXD0 Serial Port 0 Input
P3.1 TXD0 Serial Port 0 Output
P3.2 INT0 External Interrupt 0
P3.3 INT1 External Interrupt 1
P3.4 T0 Timer 0 External Input
P3.5 T1 Timer 1 External Input
P3.6 WR External Data Memory Write Strobe
P3.7 RD External Data Memory Read Strobe
42 35 EA
External Access Input, Active Low. Connect to ground to use an external ROM. Internal RAM is still accessible as determined by register settings. Connect to VCC
to use internal ROM.
51 44 VBAT
VBAT Input. Connect to the power source that maintains SRAM and RTC when VCC < VBAT. Can be connected to a 3V lithium battery or a super cap. Connect to
GND if battery will not be used with device.
27 20 RTCX2
28 21 RTCX1
Timekeeping Crystals. A 32.768kHz crystal between these pins supplies the time base for the RTC. The devices support both 6pF and 12.5pF load capacitance
crystals as selected by an SFR bit (described later). To prevent noise from
affecting the RTC, the RTCX2 and RTCX1 pins should be guard-ringed with
GND2.
2, 11, 13,
14, 40,
41
4, 6, 7,
33, 34,
47
N.C.
Not Connected. These pins should not be connected. They are reserved for use with future devices in the family.
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
COMPATIBILITY The DS87C530/DS83C530 are fully static, CMOS 8051-compatible microcontrollers designed for high
performance. While remaining familiar to 8051 users, the devices have many new features. In general,
software written for existing 8051-based systems works without modification on the
DS87C530/DS83C530. The exception is critical timing since the high-speed microcontrollers perform its
instructions much faster than the original for any given crystal selection. The DS87C530/DS83C530 run
the standard 8051 instruction set. They are not pin compatible with other 8051s due to the timekeeping
crystal.
The DS87C530/DS83C530 provide three 16-bit timer/counters, full-duplex serial port (2), 256 bytes of
direct RAM plus 1kB of extra MOVX RAM. I/O ports have the same operation as a standard 8051
product. Timers will default to a 12 clock-per-cycle operation to keep their timing compatible with
original 8051 systems. However, timers are individually programmable to run at the new 4 clocks per
cycle if desired. The PCA is not supported.
The DS87C530/DS83C530 provide several new hardware features implemented by new Special Function
Registers. A summary of these SFRs is provided below.
PERFORMANCE OVERVIEW The DS87C530/DS83C530 feature a high-speed, 8051-compatible core. Higher speed comes not just
from increasing the clock frequency, but also from a newer, more efficient design.
This updated core does not have the dummy memory cycles that are present in a standard 8051. A
conventional 8051 generates machine cycles using the clock frequency divided by 12. In the
DS87C530/DS83C530, the same machine cycle takes 4 clocks. Thus the fastest instruction, one machine
cycle, executes three times faster for the same crystal frequency. Note that these are identical instructions.
The majority of instructions on the DS87C530/DS83C530 will see the full 3-to-1 speed improvement.
Some instructions will get between 1.5 and 2.4 to 1 improvement. All instructions are faster than the
original 8051.
The numerical average of all opcodes gives approximately a 2.5 to 1 speed improvement. Improvement of
individual programs will depend on the actual instructions used. Speed-sensitive applications would make
the most use of instructions that are three times faster. However, the sheer number of 3 to 1 improved
opcodes makes dramatic speed improvements likely for any code. These architecture improvements
produce a peak instruction cycle in 121ns (8.25 MIPs). The Dual Data Pointer feature also allows the user
to eliminate wasted instructions when moving blocks of memory.
INSTRUCTION SET SUMMARY All instructions perform the same functions as their 8051 counterparts. Their effect on bits, flags, and
other status functions is identical. However, the timing of each instruction is different. This applies both
in absolute and relative number of clocks.
For absolute timing of real-time events, the timing of software loops can be calculated using a table in the
High-Speed Microcontroller User’s Guide. However, counter/timers default to run at the older 12 clocks
per increment. In this way, timer-based events occur at the standard intervals with software executing at
higher speed. Timers optionally can run at 4 clocks per increment to take advantage of faster processor
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
The relative time of two instructions might be different in the new architecture than it was previously. For
example, in the original architecture, the “MOVX A, @DPTR” instruction and the “MOV direct, direct”
instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of
time. In the DS87C530/DS83C530, the MOVX instruction takes as little as two machine cycles or eight
oscillator cycles but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While
both are faster than their original counterparts, they now have different execution times. This is because
the DS87C530/DS83C530 usually use one instruction cycle for each instruction byte. The user concerned
with precise program timing should examine the timing of each instruction for familiarity with the
changes. Note that a machine cycle now requires just 4 clocks, and provides one ALE pulse per cycle.
Many instructions require only one cycle, but some require five. In the original architecture, all were one
or two cycles except for MUL and DIV. Refer to the High-Speed Microcontroller User’s Guide for
details and individual instruction timing.
SPECIAL FUNCTION REGISTERS Special Function Registers (SFRs) control most special features of the DS87C530/DS83C530. This
allows the device to incorporate new features but remain instruction-set compatible with the 8051.
EQUATE statements can be used to define the new SFR to an assembler or compiler. All SFRs contained
in the standard 80C52 are duplicated in this device. Table 1 shows the register addresses and bit locations.
The High-Speed Microcontroller User’s Guide describes all SFRs.
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
Table 1. Special Function Register Locations * Functions not present in the 80C52 are in bold.
REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS P0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 80h
SP 81h
DPL 82h
DPH 83h
DPL1 84h
DPH1 85h
DPS 0 0 0 0 0 0 0 SEL 86h
PCON SMOD_0
SMOD0 — — GF1 GF0 STOP IDLE 87h
TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88h
TMOD GATE C/T M1 M0 GATE C/T M1 M0 89h
TL0 8Ah
TL1 8Bh
TH0 8Ch
TH1 8Dh
CKCON WD1 WD0 T2M T1M T0M MD2 MD1 MD0 8Eh
P1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 90h
EXIF IE5 IE4 IE3 IE2 XT/RG RGMD RGSL BGS 91h
TRIM E4K X12/6 TRM2 TRM2 TRM1 TRM1 TRM0 TRM0 96h
SCON0 SM0/FE_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 98h
SBUF0 99h
P2 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 A0h
IE EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 A8h
SADDR0 A9h
SADDR1 AAh
P3 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 B0h
IP — PS1 PT2 PS0 PT1 PX1 PT0 PX0 B8h
SADEN0 B9h
SADEN1 BAh
SCON1 SM0/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 C0h
SBUF1 C1h
ROMSIZE — — — — —
RMS2 RMS1 RMS0 C2h
PMR CD1 CD0 SWB — XTOFF ALEOFF DME1 DME0 C4h
STATUS PIP HIP LIP XTUP SPTA1 SPRA1 SPTA0 SPRA0 C5h
TA C7h
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 C8h
T2MOD — — — — — — T2OE DCEN C9h
RCAP2L CAh
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
Table 1. Special Function Register Locations (continued) * Functions not present in the 80C52 are in bold.
REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS TL2 CCh
TH2 CDh
PSW CY AC F0 RS1 RS0 OV FL P D0h
WDCON SMOD_1 POR EPFI PFI WDIF WTRF EWT RWT D8h
ACC E0h
EIE — —
ERTCI EWDI EX5 EX4 EX3 EX2 E8h F0h
RTASS F2h
RTAS 0 0 F3h
RTAM 0 0 F4h
RTAH 0 0 0 F5h
EIP — —
PRTCI PWDI PX5 PX4 PX3 PX2 F8h
RTCC SSCE SCE MCE HCE RTCRE RTCWE RTCIF RTCE F9h
RTCSS FAh
RTCS 0 0 FBh
RTCM 0 0 FCh
RTCH FDh
RTCD0 FEh
RTCD1 FFh
NONVOLATILE FUNCTIONS The DS87C530/DS83C530 provide two functions that are permanently powered if a user supplies an
external energy source. These are an on-chip RTC and a nonvolatile SRAM. The chip contains all related
functions and controls. The user must supply a backup source and a 32.768kHz timekeeping crystal.
REAL-TIME CLOCK The on-chip RTC keeps time of day and calendar functions. Its time base is a 32.768kHz crystal between
pins RTCX1 and RTCX2. The RTC maintains time to 1/256 of a second. It also allows a user to read (and
write) seconds, minutes, hours, day of the week, and date. Figure 2 shows the clock organization.
Timekeeping registers allow easy access to commonly needed time values. For example, software can
simply check the elapsed number of minutes by reading one register. Alternately, it can read the complete
time of day, including subseconds, in only four registers. The calendar stores its data in binary form.
While this requires software translation, it allows complete flexibility as to the exact value. A user can
start the calendar with a variety of selections since it is simply a 16-bit binary number of days. This
number allows a total range of 179 years beginning from 0000.
The RTC features a programmable alarm condition. A user selects the alarm time. When the RTC reaches
the selected value, it sets a flag. This will cause an interrupt if enabled, even in Stop mode. The alarm
consists of a comparator that matches the user value against the RTC actual value. A user can select a
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
automatically to occur once per second, once per minute, once per hour, or once per day. Enabling
interrupts with no match will generate an interrupt 256 times per second.
Software enables the timekeeper oscillator using the RTC enable bit in the RTC Control register (F9h).
This starts the clock. It can disable the oscillator to preserve the life of the backup energy-source if
unneeded. Values in the RTC Control register are maintained by the backup source through power failure.
Once enabled, the RTC maintains time for the life of the backup source even when VCC is removed.
The RTC will maintain an accuracy of 2 minutes per month at 25C. Under no circumstances are
negative voltages, of any amplitude, allowed on any pin while the device is in data retention mode
(VCC < VBAT). Negative voltages will shorten battery life, possibly corrupting the contents of internal
SRAM and the RTC.
Figure 2. Real-Time Clock
NONVOLATILE RAM The 1k x 8 on-chip SRAM can be nonvolatile if an external backup energy source is used. This allows the
device to log data or to store configuration settings. Internal switching circuits will detect the loss of VCC
and switch SRAM power to the backup source on the VBAT pin. The 256 bytes of direct RAM are not
affected by this circuit and are volatile.
CRYSTAL AND BACKUP SOURCES To use the unique functions of the DS87C530/DS83C530, a 32.768kHz timekeeping crystal and a backup
energy source are needed. The following describes guidelines for choosing these devices.
Timekeeping Crystal The DS87C530/DS83C530 can use a standard 32.768kHz crystal as the RTC time base. There are two
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
12.5pF crystal uses more power, giving a shorter battery backed life, but produces a more robust
oscillator. Bit 6 in the RTC Trim register (TRIM; 96h) must be programmed to specify the crystal type
for the oscillator. When TRIM.6 = 1, the circuit expects a 12.5pF crystal. When TRIM.6 = 0, it expects a
6pF crystal. This bit will be nonvolatile so these choices will remain while the backup source is present.
A guard ring (connected to the RTC ground) should encircle the RTCX1 and RTCX2 pins.
Backup Energy Source The DS87C530/DS83C530 use an external energy source to maintain timekeeping and SRAM data
without VCC. This source can be either a battery or 0.47F super cap and should be connected to the VBAT
pin. The nominal battery voltage is 3V. The VBAT pin will not source current. Therefore, a super cap
requires an external resistor and diode to supply charge.
The backup lifetime is a function of the battery capacity and the data retention current drain. This drain is
specified in the electrical specifications. The circuit loads the VBAT only when VCC has fallen below VBAT.
Thus the actual lifetime depends not only on the current and battery capacity, but also on the portion of
time without power. A very small lithium cell provides a lifetime of more than 10 years.
Figure 3. Internal Backup Circuit
IMPORTANT APPLICATION NOTE The pins on the DS87C530/DS83C530 are generally as resilient as other CMOS circuits. They have no
unusual susceptibility to electrostatic discharge (ESD) or other electrical transients. However, no pin on
the DS87C530/DS83C530 should ever be taken to a voltage below ground. Negative voltages on any pin can turn on internal parasitic diodes that draw current directly from the battery. If a device pin is
connected to the “outside world” where it may be handled or come in contact with electrical noise,
protection should be added to prevent the device pin from going below -0.3V. Some power supplies can
give a small undershoot on power-up, which should be prevented. Application Note 93: Design
Guidelines for Microcontrollers Incorporating NV RAM discusses how to protect the
DS87C530/DS83C530 against these conditions.
MEMORY RESOURCES
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
space SRAM is read/write accessible and is memory mapped. This on-chip SRAM is reached by the
MOVX instruction. It is not used for executable memory. The scratchpad area is 256 bytes of register
mapped RAM and is identical to the RAM found on the 80C52. There is no conflict or overlap among the
256 bytes and the 1kB as they use different addressing modes and separate instructions.
OPERATIONAL CONSIDERATION The erasure window of the windowed LCC should be covered without regard to the
programmed/unprogrammed state of the EPROM. Otherwise, the device may not meet the AC and DC
parameters listed in the data sheet.
PROGRAM MEMORY ACCESS On-chip ROM begins at address 0000h and is contiguous through 3FFFh (16kB). Exceeding the
maximum address of on-chip ROM will cause the DS87C530/DS83C530 to access off-chip memory.
However, the maximum on-chip decoded address is selectable by software using the ROMSIZE feature.
Software can cause the microcontroller to behave like a device with less on-chip memory. This is
beneficial when overlapping external memory, such as Flash, is used.
The maximum memory size is dynamically variable. Thus a portion of memory can be removed from the
memory map to access off-chip memory, then restored to access on-chip memory. In fact, all the on-chip
memory can be removed from the memory map allowing the full 64kB memory space to be addressed
from off-chip memory. ROM addresses that are larger than the selected maximum are automatically
fetched from outside the part via Ports 0 and 2. Figure 4 shows a depiction of the ROM memory map.
The ROMSIZE register is used to select the maximum on-chip decoded address for ROM. Bits RMS2,
RMS1, RMS0 have the following effect:
RMS2 RMS1 RMS0 MAXIMUM ON-CHIP ROM ADDRESS 0 0 0 0kB
0 0 1 1kB
0 1 0 2kB
0 1 1 4kB
1 0 0 8kB
1 0 1 16kB (default)
1 1 0 Invalid—reserved
1 1 1 Invalid—reserved
The reset default condition is a maximum on-chip ROM address of 16kB. Thus no action is required if
this feature is not used. When accessing external program memory, the first 16kB would be inaccessible.
To select a smaller effective ROM size, software must alter bits RMS2–RMS0. Altering these bits
requires a timed-access procedure.
Care should be taken so that changing the ROMSIZE register does not corrupt program execution. For
example, assume that a device is executing instructions from internal program memory near the 12kB
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
device will immediately jump to external program execution because program code from 4kB to 16kB
(1000h–3FFFh) is no longer located on-chip. This could result in code misalignment and execution of an
invalid instruction. The recommended method is to modify the ROMSIZE register from a location in
memory that will be internal (or external) both before and after the operation. In the above example, the
instruction which modifies the ROMSIZE register should be located below the 4kB (1000h) boundary, so
that it will be unaffected by the memory modification. The same precaution should be applied if the
internal program memory size is modified while executing from external program memory.
Off-chip memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2.
While serving as a memory bus, these pins are not I/O ports. This convention follows the standard 8051
method of expanding on-chip memory. Off-chip ROM access also occurs if the EA pin is a logic 0. EA
overrides all bit settings. The PSENsignal will go active (low) to serve as a chip enable or output enable
when Ports 0 and 2 fetch from external ROM.
Figure 4. ROM Memory Map
DATA MEMORY ACCESS Unlike many 8051 derivatives, the DS87C530/DS83C530 contain on-chip data memory. The devices also
contain the standard 256 bytes of RAM accessed by direct instructions. These areas are separate. The
MOVX instruction accesses the on-chip data memory. Although physically on-chip, software treats this
area as though it was located off-chip. The 1kB of SRAM is between address 0000h and 03FFh.
Access to the on-chip data RAM is optional under software control. When enabled by software, the data
SRAM is between 0000h and 03FFh. Any MOVX instruction that uses this area will go to the on-chip
RAM while enabled. MOVX addresses greater than 03FFh automatically go to external memory through
Ports 0 and 2.
When disabled, the 1kB memory area is transparent to the system memory map. Any MOVX directed to
the space between 0000h and FFFFh goes to the expanded bus on Ports 0 and 2. This also is the default
condition. This default allows the DS87C530/DS83C530 to drop into an existing system that uses these
addresses for other hardware and still have full compatibility.
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
The on-chip data area is software selectable using 2 bits in the Power Management Register at location
C4h. This selection is dynamically programmable. Thus access to the on-chip area becomes transparent to
reach off-chip devices at the same addresses. The control bits are DME1 (PMR.1) and DME0 (PMR.0).
They have the following operation:
Table 2. Data Memory Access Control
DME1 DME0 DATA MEMORY ADDRESS MEMORY FUNCTION 0 0000h–FFFFh External Data Memory (default condition)
0000h–03FFh Internal SRAM Data Memory 0 1 0400h–FFFFh External Data Memory
1 0 Reserved Reserved
0000h–03FFh Internal SRAM Data Memory
0400h–FFFBh Reserved—no external access
FFFCh Read access to the status of lock bits 1 1
FFFDh–FFFh Reserved—no external access
Notes on the status byte read at FFFCh with DME1, 0 = 1, 1: Bits 2-0 reflect the programmed status of
the security lock bits LB2–LB0. They are individually set to a logic 1 to correspond to a security lock bit
that has been programmed. These status bits allow software to verify that the part has been locked before
running if desired. The bits are read-only.
Note: After internal MOVX SRAM has been initialized, changing bits DEM0/1 has no effect on the
contents of the SRAM.
STRETCH MEMORY CYCLE The DS87C530/DS83C530 allow software to adjust the speed of off-chip data memory access. The
microcontrollers can perform the MOVX in as few as two instruction cycles. The on-chip SRAM uses
this speed and any MOVX instruction directed internally uses two cycles. However, the time can be
stretched for interface to external devices. This allows access to both fast memory and slow memory or
peripherals with no glue logic. Even in high-speed systems, it may not be necessary or desirable to
perform off-chip data memory access at full speed. In addition, there are a variety of memory-mapped
peripherals such as LCDs or UARTs that are slow.
The Stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below.
It allows the user to select a Stretch value between 0 and 7. A Stretch of 0 will result in a two-machine
cycle MOVX. A Stretch of 7 will result in a MOVX of nine machine cycles. Software can dynamically
change this value depending on the particular memory or peripheral.
On reset, the Stretch value will default to a 1, resulting in a three-cycle MOVX for any external access.
Therefore, off-chip RAM access is not at full speed. This is a convenience to existing designs that may
not have fast RAM in place. Internal SRAM access is always at full speed regardless of the Stretch
setting. When desiring maximum speed, software should select a Stretch value of 0. When using very
slow RAM or peripherals, select a larger Stretch value. Note that this affects data memory only and the
only way to slow program memory (ROM) access is to use a slower crystal.
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
Using a Stretch value between 1 and 7 causes the microcontroller to stretch the read/write strobe and all
related timing. Also, setup and hold times are increased by 1 clock when using any Stretch greater than 0.
This results in a wider read/write strobe and relaxed interface timing, allowing more time for
memory/peripherals to respond. The timing of the variable speed MOVX is in the Electrical
Specifications section. Table 3 shows the resulting strobe widths for each Stretch value. The memory
Stretch uses the Clock Control Special Function Register at SFR location 8Eh. The Stretch value is
selected using bits CKCON.2–0. In the table, these bits are referred to as M2 through M0. The first
Stretch (default) allows the use of common 120ns RAMs without dramatically lengthening the memory
access.
Table 3. Data Memory Cycle Stretch Values
CKCON.2–0
M2 M1 M0 MEMORY CYCLES RD OR WR STROBE
WIDTH IN CLOCKS
STROBE WIDTH TIME
AT 33MHz
(ns) 0 0 0 2 (forced internal) 2 60
0 0 1 3 (default external) 4 121
0 1 0 4 8 242
0 1 1 5 12 364
1 0 0 6 16 485
1 0 1 7 20 606
1 1 0 8 24 727
1 1 1 9 28 848
DUAL DATA POINTER The timing of block moves of data memory is faster using the Dual Data Pointer (DPTR). The standard
8051 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the
DS87C530/DS83C530, the standard data pointer is called DPTR, located at SFR addresses 82h and 83h.
These are the standard locations. Using DPTR requires no modification of standard code. The new DPTR
at SFR 84h and 85h is called DPTR1. The DPTR Select bit (DPS) chooses the active pointer. Its location
is the lsb of the SFR location 86h. No other bits in register 86h have any effect and are 0. The user
switches between data pointers by toggling the lsb of register 86h. The increment (INC) instruction is the
fastest way to accomplish this. All DPTR-related instructions use the currently selected DPTR for any
activity. Therefore it takes only one instruction to switch from a source to a destination address. Using the
Dual Data Pointer saves code from needing to save source and destination addresses when doing a block
move. The software simply switches between DPTR and 1 once software loads them. The relevant
register locations are as follows.
DPL 82h Low byte original DPTR
DPH 83h High byte original DPTR
DPL1 84h Low byte new DPTR
DPH1 85h High byte new DPTR
DPS 86h DPTR Select (lsb)
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
POWER MANAGEMENT Along with the standard Idle and power-down (Stop) modes of the standard 80C52, the
DS87C530/DS83C530 provide a new Power Management Mode. This mode allows the processor to
continue functioning, yet to save power compared with full operation. The DS87C530/DS83C530 also
feature several enhancements to Stop mode that make it more useful.
POWER MANAGEMENT MODE (PMM) Power Management Mode offers a complete scheme of reduced internal clock speeds that allow the CPU
to run software but to use substantially less power. During default operation, the DS87C530/DS83C530
use four clocks per machine cycle. Thus the instruction cycle rate is (Clock/4). At 33MHz crystal speed,
the instruction cycle speed is 8.25MHz (33/4). In PMM, the microcontroller continues to operate but uses
an internally divided version of the clock source. This creates a lower power state without external
components. It offers a choice of two reduced instruction cycle speeds (and two clock sources - discussed
below). The speeds are (Clock/64) and (Clock/1024).
Software is the only mechanism to invoke the PMM. Table 4 illustrates the instruction cycle rate in PMM
for several common crystal frequencies. Since power consumption is a direct function of operating speed,
PMM 1 eliminates most of the power consumption while still allowing a reasonable speed of processing.
PMM 2 runs very slowly and provides the lowest power consumption without stopping the CPU. This is
illustrated in Table 5.
Note that PMM provides a lower power condition than Idle mode. This is because in Idle, all clocked
functions such as timers run at a rate of crystal divided by 4. Since wake-up from PMM is as fast as or
faster than from Idle and PMM allows the CPU to operate (even if doing NOPs), there is little reason to
use Idle mode in new designs.
Table 4. Machine Cycle Rate
CRYSTAL SPEED
(MHz)
FULL OPERATION
(4 CLOCKS)
(MHz)
PMM1
(64 CLOCKS)
(kHz)
PMM2
(1024 CLOCKS)
(kHz) 11.0592 2.765 172.8 10.8
16 4.00 250.0 15.6
25 6.25 390.6 24.4
33 8.25 515.6 32.2
Table 5. Typical Operating Current in PMM
CRYSTAL SPEED
(MHz)
FULL OPERATION
(4 CLOCKS)
(mA)
PMM1
(64 CLOCKS)
(mA)
PMM2
(1024 CLOCKS)
(mA) 11.0592 13.1 5.3 4.8
16 17.2 6.4 5.6
25 25.7 8.1 7.0
33 32.8 9.8 8.2
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
CRYSTAL-LESS PMM A major component of power consumption in PMM is the crystal amplifier circuit. The
DS87C530/DS83C530 allow the user to switch CPU operation to an internal ring oscillator and turn off
the crystal amplifier. The CPU would then have a clock source of approximately 2MHz to 4MHz, divided
by either 4, 64, or 1024. The ring is not accurate, so software cannot perform precision timing. However,
this mode allows an additional saving of between 0.5mA and 6.0mA, depending on the actual crystal
frequency. While this saving is of little use when running at 4 clocks per instruction cycle, it makes a
major contribution when running in PMM1 or PMM2.
PMM OPERATION Software invokes the PMM by setting the appropriate bits in the SFR area. The basic choices are divider
speed and clock source. There are three speeds (4, 64, and 1024) and two clock sources (crystal, ring).
Both the decisions and the controls are separate. Software will typically select the clock speed first. Then,
it will perform the switch to ring operation if desired. Lastly, software can disable the crystal amplifier if
desired.
There are two ways of exiting PMM. Software can remove the condition by reversing the procedure that
invoked PMM or hardware can (optionally) remove it. To resume operation at a divide-by-4 rate under
software control, simply select 4 clocks per cycle, and then crystal-based operation if relevant. When
disabling the crystal as the time base in favor of the ring oscillator, there are timing restrictions associated
with restarting the crystal operation. Details are described below.
There are three registers containing bits that are concerned with PMM functions. They are Power
Management Register (PMR; C4h), Status (STATUS; C5h), and External Interrupt Flag (EXIF; 91h)
Clock Divider Software can select the instruction cycle rate by selecting bits CD1 (PMR.7) and CD0 (PMR.6) as
follows:
CD1 CD0 CYCLE RATE 0 0 Reserved 1 4 clocks (default)
1 0 64 clocks
1 1 1024 clocks
The selection of instruction cycle rate will take effect after a delay of one instruction cycle. Note that the
clock divider choice applies to all functions including timers. Since baud rates are altered, it will be
difficult to conduct serial communication while in PMM. There are minor restrictions on accessing the
clock selection bits. The processor must be running in a 4-clock state to select either 64 (PMM1) or 1024
(PMM2) clocks. This means software cannot go directly from PMM1 to PMM2 or visa versa. It must
return to a 4-clock rate first.
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
Switchback To return to a 4-clock rate from PMM, software can simply select the CD1 and CD0 clock control bits to
the 4 clocks per cycle state. However, the DS87C530/DS83C530 provide several hardware alternatives
for automatic Switchback. If Switchback is enabled, then the device will automatically return to a 4-clock
per cycle speed when an interrupt occurs from an enabled, valid external interrupt source. A Switchback
will also occur when a UART detects the beginning of a serial start bit if the serial receiver is enabled
(REN = 1). Note the beginning of a start bit does not generate an interrupt; this occurs on reception of a
complete serial word. The automatic Switchback on detection of a start bit allows hardware to correct
baud rates in time for a proper serial reception. A Switchback will also occur when a byte is written to the
SBUF0 or SBUF1 for transmission.
Switchback is enabled by setting the SWB bit (PMR.5) to a 1 in software. For an external interrupt,
Switchback will occur only if the interrupt source could really generate the interrupt. For example, if
INT0 is enabled but has a low priority setting, then Switchback will not occur on INT0 if the CPU is
servicing a high priority interrupt.
Status Information in the Status register assists decisions about switching into PMM. This register contains
information about the level of active interrupts and the activity on the serial ports.
The DS87C530/DS83C530 support three levels of interrupt priority. These levels are Power-fail, High,
and Low. Bits STATUS.7–5 indicate the service status of each level. If PIP (Power-fail Interrupt Priority;
STATUS. 7) is 1, then the processor is servicing this level. If either HIP (High Interrupt Priority;
STATUS.6) or LIP (Low Interrupt Priority; STATUS.5) is high, then the corresponding level is in
service.
Software should not rely on a lower priority level interrupt source to remove PMM (Switchback) when a
higher level is in service. Check the current priority service level before entering PMM. If the current
service level locks out a desired Switchback source, then it would be advisable to wait until this condition
clears before entering PMM.
Alternately, software can prevent an undesired exit from PMM by entering a low priority interrupt service
level before entering PMM. This will prevent other low priority interrupts from causing a Switchback.
Status also contains information about the state of the serial ports. Serial Port Zero Receive Activity
(SPRA0; STATUS.0) indicates a serial word is being received on Serial Port 0 when this bit is set to a 1.
Serial Port 0 Transmit Activity (SPTA0; STATUS.1) indicates that the serial port is still shifting out a
serial transmission. STATUS.2 and STATUS.3 provide the same information for Serial Port 1,
respectively. These bits should be interrogated before entering PMM1 or PMM2 to ensure that no serial
port operations are in progress. Changing the clock divisor rate during a serial transmission or reception
will corrupt the operation.
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
Crystal/Ring Operation The DS87C530/DS83C530 allow software to choose the clock source as an independent selection from
the instruction cycle rate. The user can select crystal-based or ring oscillator-based operation under
software control. Power-on reset default is the crystal (or external clock) source. The ring may save
power depending on the actual crystal speed. To save still more power, software can then disable the
crystal amplifier. This process requires two steps. Reversing the process also requires two steps.
The XT/RG bit (EXIF.3) selects the crystal or ring as the clock source. Setting XT/RG = 1 selects the
crystal. Setting XT/RG = 0 selects the ring. The RGMD (EXIF.2) bit serves as a status bit by indicating
the active clock source. RGMD = 0 indicates the CPU is running from the crystal. RGMD = 1 indicates it
is running from the ring. When operating from the ring, disable the crystal amplifier by setting the
XTOFF bit (PMR.3) to a 1. This can only be done when XT/RG = 0.
When changing the clock source, the selection will take effect after a one-instruction-cycle delay. This
applies to changes from crystal to ring and vise versa. However, this assumes that the crystal amplifier is
running. In most cases, when the ring is active, software previously disabled the crystal to save power. If
ring operation is being used and the system must switch to crystal operation, the crystal must first be
enabled. Set the XTOFF bit to 0. At this time, the crystal oscillation will begin. The
DS87C530/DS83C530 then provide a warm-up delay to make certain that the frequency is stable.
Hardware will set the XTUP bit (STATUS.4) to 1 when the crystal is ready for use. Then software should
write XT/RG to 1 to begin operating from the crystal. Hardware prevents writing XT/RG to 1 before
XTUP = 1. The delay between XTOFF = 0 and XTUP = 1 will be 65,536 crystal clocks in addition to the
crystal cycle startup time.
Switchback has no affect on the clock source. If software selects a reduced clock divider and enables the
ring, a Switchback will only restore the divider speed. The ring will remain as the time base until altered
by software. If there is serial activity, Switchback usually occurs with enough time to create proper baud
rates. This is not true if the crystal is off and the CPU is running from the ring. If sending a serial
character that wakes the system from crystal-less PMM, then it should be a dummy character of no
importance with a subsequent delay for crystal startup.
Table 6 is a summary of the bits relating to PMM and its operation. The flow chart below illustrates a
typical decision set associated with PMM.
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
Table 6. PMM Control and Status Bit Summary
NAME LOCATION FUNCTION RESET WRITE ACCESS XT/RG EXIF.3 Control. XT/RG=1, runs from crystal or external
clock; XT/RG=0, runs from internal ring oscillator. X
0 to 1 only when
XTUP = 1 and
XTOFF= 0
RGMD EXIF.2 Status. RGMD=1, CPU clock = ring; RGMD = 0,
CPU clock = crystal. 0 None
CD1, CD0 PMR7, PMR.6 Control. CD1, 0 = 01, 4 clocks; CS1, 0 = 10, PMM1;
CD1, 0 = 11, PMM2. 0, 1
Write CD1, 0 = 10 or
11 only from CD1, 0 =
01
SWB PMR.5 Control. SWB = 1, hardware invokes switchback to 4
clocks, SWB = 0, no hardware switchback. 0 Unrestricted
XTOFF PMR.3 Control. Disables crystal operation after ring is
selected. 0 1 only when XT/RG
= 0
PIP STATUS.7 Status. 1 indicates a power-fail interrupt in service. 0 None
HIP STATUS.6 Status. 1 indicates high priority interrupt in service. 0 None
LIP STATUS.5 Status. 1 indicates low priority interrupt in service. 0 None
XTUP STATUS.4 Status. 1 indicates that the crystal has stabilized. 1 None
SPTA1 STATUS.3 Status. Serial transmission on serial port 1. 0 None
SPRA1 STATUS.2 Status. Serial word reception on serial port 1. 0 None
SPTA0 STATUS.1 Status. Serial transmission on serial port 0. 0 None
SPRA0 STATUS.0 Status. Serial word reception on serial port 0. 0 None
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
Figure 5. Invoking and Clearing PMM DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
IDLE MODE Setting the lsb of the Power Control register (PCON; 87h) invokes the Idle mode. Idle will leave internal
clocks, serial ports and timers running. Power consumption drops because the CPU is not active. Since
clocks are running, the Idle power consumption is a function of crystal frequency. It should be
approximately one-half the operational power at a given frequency. The CPU can exit the Idle state with
any interrupt or a reset. Idle is available for backward software compatibility. The system can now reduce
power consumption to below Idle levels by using PMM1 or PMM2 and running NOPs.
STOP MODE ENHANCEMENTS Setting bit 1 of the Power Control register (PCON; 87h) invokes the Stop mode. Stop mode is the lowest
power state since it turns off all internal clocking. The ICC of a standard Stop mode is approximately 1 A
but is specified in the Electrical Specifications. The CPU will exit Stop mode from an external interrupt
or a reset condition. Internally generated interrupts (timer, serial port, watchdog) are not useful since they
require clocking activity. One exception is that a RTC interrupt can cause the device to exit Stop mode.
This provides a very power efficient way of performing infrequent yet periodic tasks.
The DS87C530/DS83C530 provide two enhancements to the Stop mode. As documented below, the
device provides a bandgap reference to determine Power-fail Interrupt and Reset thresholds. The default
state is that the bandgap reference is off while in Stop mode. This allows the extremely low-power state
mentioned above. A user can optionally choose to have the bandgap enabled during Stop mode. With the
bandgap reference enabled, PFI and Power-fail Reset are functional and are a valid means for leaving
Stop mode. This allows software to detect and compensate for a brownout or power supply sag, even
when in Stop mode.
In Stop mode with the bandgap enabled, ICC will be approximately 50A compared with 1A with the
bandgap off. If a user does not require a Power-fail Reset or Interrupt while in Stop mode, the bandgap
can remain disabled. Only the most power sensitive applications should turn off the bandgap, as this
results in an uncontrolled power-down condition.
The control of the bandgap reference is located in the Extended Interrupt Flag register (EXIF; 91h).
Setting BGS (EXIF.0) to a 1 will keep the bandgap reference enabled during Stop mode. The default or
reset condition is with the bit at a logic 0. This results in the bandgap being off during Stop mode. Note
that this bit has no control of the reference during full power, PMM, or Idle modes.
The second feature allows an additional power saving option while also making Stop easier to use. This is
the ability to start instantly when exiting Stop mode. It is the internal ring oscillator that provides this
feature. This ring can be a clock source when exiting Stop mode in response to an interrupt. The benefit
of the ring oscillator is as follows.
Using Stop mode turns off the crystal oscillator and all internal clocks to save power. This requires that
the oscillator be restarted when exiting Stop mode. Actual startup time is crystal-dependent, but is
normally at least 4ms. A common recommendation is 10ms. In an application that will wake up, perform
a short operation, then return to sleep, the crystal startup can be longer than the real transaction. However,
the ring oscillator will start instantly. Running from the ring, the user can perform a simple operation and
return to sleep before the crystal has even started. If a user selects the ring to provide the startup clock and
the processor remains running, hardware will automatically switch to the crystal once a power-on reset
interval (65,536 clocks) has expired. Hardware uses this value to assure proper crystal start even though
