DS87C530-ENL ,EPROM MICRO WITH REAL TIME CLOCKapplications. It also provides sev- sor slows.eral peripherals found on other Dallas High–SpeedMicr ..
DS87C530-KCL ,EPROM MICRO WITH REAL TIME CLOCKFEATURES PACKAGE OUTLINE7 147• 80C52 Compatible– 8051 Instruction set8 46– Four 8–bit I/O ports– Th ..
DS87C530QCL ,33 MHz, EPROM/ROM microcontroller with real-time clockapplications. They also provide several peripherals found on other Dallas high-speed microcontrolle ..
DS87C530-QCL ,EPROM/ROM Microcontrollers with Real-Time ClockBLOCK DIAGRAM Figure 1RTCX1 RTCX2 GND VV CC2BATVCC BATTERY REAL TIMECONTROL CLOCK1K X 8ACCUMULATOR ..
DS87C530QCL. ,33 MHz, EPROM/ROM microcontroller with real-time clockFeatures Selects Effective On-Chip ROM Size from DALLAS 0 to 16kB DS87C530 Allows Access to En ..
DS87C530-QCL+ ,EPROM Microcontrollers with Real-Time ClockFEATURES PIN CONFIGURATIONS 80C52 Compatible TOP VIEW 8051 Instruction-Set Compatible Four 8-B ..
ECH8653 ,N-Channel Power MOSFET, 20V, 7.5A, 20mOhm, Dual ECH8Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage V 20 VDSS ..
ECH8657 ,N-Channel Power MOSFET, 35V, 4.5A, 59mOhm, Dual ECH8Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage V 35 VDSS ..
DS87C530-ENL-DS87C530-KCL-DS87C530-QCL
EPROM MICRO WITH REAL TIME CLOCK
Copyright 1995 by Dallas Semiconductor Corporation.All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer toDallas Semiconductor data books.
DS87C530EPROM Micro with Real Time Clock
DS87C530
022197 1/40
FEATURES80C52 Compatible8051 Instruction setFour 8–bit I/O portsThree 16–bit timer/counters256 bytes scratchpad RAMLarge On–chip Memory16KB EPROM (OTP)1KB extra on–chip SRAM for MOVX
ROMSIZETM FeatureSelects effective on–chip ROM size from
0 to 16KBAllows access to entire external memory mapDynamically adjustable by softwareUseful as boot block for external FlashNonvolatile Functions
On–chip Real Time Clock w/ Alarm InterruptBattery backup support of 1KB SRAMHigh–Speed Architecture4 clocks/machine cycle (8051 = 12)Runs DC to 33 MHz clock ratesSingle–cycle instruction in 121 nsDual data pointerOptional variable length MOVX to access
fast/slow RAM /peripheralsPower Management ModeProgrammable clock source saves powerRuns from (crystal/64) or (crystal/1024)Provides automatic hardware and software exitEMI Reduction Mode disables ALEHigh integration controller includes:Power–fail resetEarly–warning power–fail interruptProgrammable Watchdog timerTwo full–duplex hardware serial ports14 total interrupt sources with 6 external
PACKAGE OUTLINE52–PIN PLCC
52–PIN CER QUAD
52–PIN TQFP OUTLINE
DALLASDS87C530
DESCRIPTIONThe DS87C530 is an 8051 compatible microcontroller
based on the Dallas High Speed core. It uses four clocks
per instruction cycle instead of 12 used by the standard
8051. It also provides a unique mix of peripherals not
widely available on other processors. They include an
on–chip Real Time Clock (RTC) and battery back up
support for an on–chip 1K x 8 SRAM. The new Power
Management Mode allows software to select reduced
power operation while still processing.
DS87C530
022197 2/40combination of high performance microcontroller
core, real time clock, battery backed SRAM, and power
management makes the DS87C530 ideal for instru-
ments and portable applications. It also provides sev-
eral peripherals found on other Dallas High–Speed
Microcontrollers. These include two independent serial
ports, two data pointers, on–chip power monitor with
brown–out detection and a watchdog timer.
Power Management Mode (PMM) allows software to
select a slower CPU clock. While default operation uses
four clocks per machine cycle, the PMM runs the pro-
cessor at 64 or 1024 clocks per cycle. There is a corre-
sponding drop in power consumption when the proces-
sor slows.
Note: The DS87C530 is a monolithic device. A user
must supply an external battery or super–cap and a
32.768 KHz timekeeping crystal to have permanently
powered timekeeping or nonvolatile RAM. The
DS87C530 provides all the support and switching cir-
cuitry needed to manage these resources.
ORDERING INFORMATION
DS87C530 BLOCK DIAGRAM Figure 1P1.0–P1.7
P3.0–P3.7
AD0–AD7
P2.0–P2.7
GND
AL2
AL1ALE
PSEN
RST
VCC
VBATRTCX1RTCX2GNDVCC2
DS87C530
022197 3/40
PIN DESCRIPTION Table 1
DS87C530
022197 4/40
DS87C530
022197 5/40
COMPATIBILITYThe DS87C530 is a fully static CMOS 8051 compatible
microcontroller designed for high performance. While
remaining familiar to 8051 users, it has many new fea-
tures. In general, software written for existing 8051
based systems works without modification on the
DS87C530. The exception is critical timing since the
High Speed Micro performs its instructions much faster
than the original for any given crystal selection. The
DS87C530 runs the standard 8051 instruction set. It is
not pin compatible with other 8051s due to the time-
keeping crystal.
The DS87C530 provides three 16–bit timer/counters,
full–duplex serial port (2), 256 bytes of direct RAM plus
1KB of extra MOVX RAM. I/O ports have the same
operation as a standard 8051 product. Timers will
default to a 12 clock per cycle operation to keep their
timing compatible with original 8051 systems. However,
timers are individually programmable to run at the new 4
clocks per cycle if desired. The PCA is not supported.
The DS87C530 provides several new hardware fea-
tures implemented by new Special Function Registers.
A summary of these SFRs is provided below.
PERFORMANCE OVERVIEWThe DS87C530 features a high speed 8051 compatible
core. Higher speed comes not just from increasing the
clock frequency, but from a newer, more efficient
design.
This updated core does not have the dummy memory
cycles that are present in a standard 8051. A conven-
tional 8051 generates machine cycles using the clock
frequency divided by 12. In the DS87C530, the same
machine cycle takes four clocks. Thus the fastest
instruction, 1 machine cycle, executes three times
faster for the same crystal frequency. Note that these
are identical instructions. The majority of instructions on
the DS87C530 will see the full 3 to 1 speed improve-
ment. Some instructions will get between 1.5 and 2.4 to
1 improvement. All instructions are faster than the origi-
nal 8051.
The numerical average of all opcodes gives approxi-
mately a 2.5 to 1 speed improvement. Improvement of
individual programs will depend on the actual instruc-
tions used. Speed sensitive applications would make
the most use of instructions that are three times faster.
However, the sheer number of 3 to 1 improved opcodes
makes dramatic speed improvements likely for any
code. These architecture improvements and 0.8 μm
CMOS produce a peak instruction cycle in 121 ns (8.25
MIPs). The Dual Data Pointer feature also allows the
user to eliminate wasted instructions when moving
blocks of memory.
INSTRUCTION SET SUMMARYAll instructions in the DS87C530 perform the same
functions as their 8051 counterparts. Their effect on
bits, flags, and other status functions is identical. How-
ever, the timing of each instruction is different. This
applies both in absolute and relative number of clocks.
For absolute timing of real–time events, the timing of
software loops can be calculated using a table in the
High–Speed Microcontroller User’s Guide. However,
counter/timers default to run at the older 12 clocks per
increment. In this way, timer–based events occur at the
standard intervals with software executing at higher
speed. Timers optionally can run at 4 clocks per incre-
ment to take advantage of faster processor operation.
The relative time of two instructions might be different in
the new architecture than it was previously. For exam-
ple, in the original architecture, the “MOVX A, @DPTR”
instruction and the “MOV direct, direct” instruction used
DS87C530
022197 6/40
two machine cycles or 24 oscillator cycles. Therefore,
they required the same amount of time. In the
DS87C530, the MOVX instruction takes as little as two
machine cycles or eight oscillator cycles but the “MOV
direct, direct” uses three machine cycles or 12 oscillator
cycles. While both are faster than their original counter-
parts, they now have different execution times. This is
because the DS87C530 usually uses one instruction
cycle for each instruction byte. The user concerned with
precise program timing should examine the timing of
each instruction for familiarity with the changes. Note
that a machine cycle now requires just four clocks, and
provides one ALE pulse per cycle. Many instructions
require only one cycle, but some require five. In the orig-
inal architecture, all were one or two cycles except for
MUL and DIV. Refer to the High–Speed Microcontroller
User’s Guide for details and individual instruction tim-
ing.
SPECIAL FUNCTION REGISTER LOCATIONS Table 2* Functions not present in the 80C52 are in bold
DS87C530
022197 7/40
RTCIFDS87C530
022197 8/40
NONVOLATILE FUNCTIONSThe DS87C530 provides two functions that are perma-
nently powered if a user supplies an external energy
source. These are an on–chip real time clock and a non-
volatile SRAM. The chip contains all related functions
and controls. The user must supply a backup source
and a 32.768 KHz timekeeping crystal.
REAL TIME CLOCKThe on–chip Real Time Clock (RTC) keeps time of day
and calendar functions. Its timebase is a 32.768 KHz
crystal between pins RTCX1 and RTCX2. The RTC
maintains time to 1/256 of a second. It also allows a user
to read (and write) seconds, minutes, hours, day of the
week, and date. The clock organization is shown in Fig-
ure 2.
Timekeeping registers allow easy access to commonly
needed time values. For example, software can simply
check the elapsed number of minutes by reading one
register. Alternately, it can read the complete time of
day, including subseconds, in only four registers. The
calendar stores its data in binary form. While this
requires software translation, it allows complete flexibil-
ity as to the exact value. A user can start the calendar
with a variety of selections since it is simply a 16–bit
binary number of days. This number allows a total range
of 179 years beginning from 0000.
The RTC features a programmable alarm condition. A
user selects the alarm time. When the RTC reaches the
selected value, it sets a flag. This will cause an interrupt
if enabled, even in Stop mode. The alarm consists of a
comparator that matches the user value against the
RTC actual value. A user can select a match for one or
more of the sub–seconds, seconds, minutes, or hours.
This allows an interrupt automatically to occur once per
second, once per minute, once per hour, or once per
day. Enabling interrupts with no match will generate an
interrupt 256 times per second.
Software enables the timekeeper oscillator using the
RTC Enable bit in the RTC Control register (F9h). This
starts the clock. It can disable the oscillator to preserve
the life of the backup energy–source if unneeded. Val-
ues in the RTC Control register are maintained by the
backup source through power failure. Once enabled,
the RTC maintains time for the life of the backup source
even when VCC is removed.
The RTC will maintain an accuracy of ±2 minutes per
month at 25°C. Under no circumstances are negative
voltages, of any amplitude, allowed on any pin while the
device is in data retention mode (VCC < VBAT). Negative
voltages will shorten battery life, possibly corrupting the
contents of internal SRAM and the RTC.
REAL TIME CLOCK Figure 2
DS87C530
022197 9/40
NONVOLATILE RAMThe 1K x 8 on–chip SRAM can be nonvolatile. An exter-
nal backup energy–source will maintain the SRAM con-
tents through power failure. This allows the DS87C530
to log data or to store configuration settings. Internal
switching circuits will detect the loss of VCC and switch
SRAM power to the backup source on the VBAT pin. The
256 bytes of direct RAM are not affected by this circuit
and are volatile.
CRYSTAL AND BACKUP SOURCESTo use the unique functions of the DS87C530, two
external components are needed. These are a 32.768
KHz timekeeping crystal and a backup energy–source.
The following describes guidelines for choosing these
devices.
Timekeeping CrystalThe DS87C530 can use a standard 32.768 KHz crystal
as the RTC time base. There are two versions of stan-
dard crystals available, with 6 pF and 12.5 pF load
capacitance. The tradeoff is that the 6 pF uses less
power, giving longer life while VCC is off, but is more sen-
sitive to noise and board layout. The 12.5 pF crystal
uses more power, giving a shorter battery backed life,
but produces a more robust oscillator. Bit 6 in the RTC
Trim register (TRIM; 96h) must be programmed to spec-
ify the crystal type for the oscillator. When TRIM.6 = 1,
the circuit expects a 12.5 pF crystal. When TRIM.6 = 0, it
expects a 6 pF crystal. As mentioned above, this bit will
be nonvolatile so these choices will remain while the
backup source is present. A guard ring (connected to
the Real Time Clock ground) should encircle the RTCX1
and RTCX2 pins.
Backup Energy SourceThe DS87C530 uses an external energy source to
maintain timekeeping and SRAM data without VCC. This
source can be either a battery or 0.47 F super cap and
should be connected to the VBAT pin. The nominal bat-
tery voltage is 3V. The VBAT pin will not source current.
Therefore, a super cap requires an external resistor and
diode to supply charge.
The backup lifetime is a function of the battery capacity
and the data retention current drain. This drain is speci-
fied in the electrical specifications. The circuit loads the
VBAT only when VCC has fallen below VBAT. Thus the
actual lifetime depends not only on the current and bat-
tery capacity, but also on the portion of time without
power. A very small lithium cell provides a lifetime of
more than 10 years.
DS87C530
022197 10/40
INTERNAL BACKUP CIRCUIT Figure 3VCC (SRAM AND RTC)
1.5KΩ
IMPORTANT APPLICATION NOTEThe pins on the DS87C530 are generally as resilient as other CMOS circuits. They have no unusual susceptibility to
electrostatic discharge (ESD) or other electrical transients. However, no pin on the DS87C530 should ever be tak-
en to a voltage below ground. Negative voltages on any pin can turn on internal parasitic diodes that draw currentdirectly from the battery. If a device pin is connected to the “outside world” where it may be handled or come in contact
with electrical noise, protection should be added to prevent the device pin from going below -0.3V. Some power sup-
plies can give a small undershoot on power up, which should be prevented. Application Note 93, “Design Guidelines
for Microcontrollers Incorporating NVRAM”, discusses how to protect the DS87C530 against these conditions.
DS87C530
022197 11/40
MEMORY RESOURCESLike the 8051, the DS87C530 uses three memory
areas. These are program (ROM), data (RAM), and
scratchpad RAM (registers). The DS87C530 contains
on–chip quantities of all three areas.
The total memory configuration of the DS87C530 is
16KB of ROM, 1KB of data SRAM and 256 bytes of
scratchpad or direct RAM. The 1KB of data space
SRAM is read/write accessible and is memory mapped.
This on–chip SRAM is reached by the MOVX instruc-
tion. It is not used for executable memory. The scratch-
pad area is 256 bytes of register mapped RAM and is
identical to the RAM found on the 80C52. There is no
conflict or overlap among the 256 bytes and the 1KB as
they use different addressing modes and separate
instructions.
OPERATIONAL CONSIDERATIONThe erasure window should be covered without regard
to the programmed/unprogrammed state of the
EPROM. Otherwise, the device may not meet the AC
and DC parameters listed in the datasheet.
PROGRAM MEMORY ACCESSOn–chip ROM begins at address 0000h and is contigu-
ous through 3FFFh (16KB). Exceeding the maximum
address of on–chip ROM will cause the DS87C530 to
access off–chip memory. However, the maximum on–
chip decoded address is selectable by software using
the ROMSIZETM feature. Software can cause the
DS87C530 to behave like a device with less on–chip
memory. This is beneficial when overlapping external
memory, such as Flash, is used.
The maximum memory size is dynamically variable.
Thus a portion of memory can be removed from the
memory map to access off–chip memory, then restored
to access on–chip memory. In fact, all of the on–chip
memory can be removed from the memory map allow-
ing the full 64KB memory space to be addressed from
off–chip memory. ROM addresses that are larger than
the selected maximum are automatically fetched from
outside the part via Ports 0 and 2. A depiction of the
ROM memory map is shown in Figure 4.
The ROMSIZE register is used to select the maximum
on–chip decoded address for ROM. Bits RMS2, RMS1,
RMS0 have the following affect:
RMS2RMS1RMS0
Maximum on–chip
ROM Address000KB011KB102KB114KB008KB0116KB (default)10Invalid – reserved11Invalid – reserved
The reset default condition is a maximum on–chip ROM
address of 16KB. Thus no action is required if this fea-
ture is not used. When accessing external program
memory, the first 16KB would be inaccessible. To select
a smaller effective ROM size, software must alter bits
RMS2–RMS0. Altering these bits requires a Timed
Access procedure as explained below.
Care should be taken so that changing the ROMSIZE
register does not corrupt program execution. For exam-
ple, assume that a DS87C520 is executing instructions
from internal program memory near the 12KB boundary
(~3000h) and that the ROMSIZE register is currently
configured for a 16KB internal program space. If soft-
ware reconfigures the ROMSIZE register to 4KB
(0000h–0FFFh) in the current state, the device will
immediately jump to external program execution
because program code from 4KB to 16KB
(1000h–3FFFh) is no longer located on–chip. This
could result in code misalignment and execution of an
invalid instruction. The recommended method is to
modify the ROMSIZE register from a location in memory
that will be internal (or external) both before and after the
operation. In the above example, the instruction which
modifies the ROMSIZE register should be located
below the 4KB (1000h) boundary, so that it will be unaf-
fected by the memory modification. The same precau-
tion should be applied if the internal program memory
size is modified while executing from external program
memory.
Off–chip memory is accessed using the multiplexed
address/data bus on P0 and the MSB address on P2.
While serving as a memory bus, these pins are not I/O
ports. This convention follows the standard 8051
method of expanding on–chip memory. Off–chip ROM
access also occurs if the EA pin is a logic 0. EA over-
rides all bit settings. The PSEN signal will go active (low)
to serve as a chip enable or output enable when Ports 0
and 2 fetch from external ROM.
DS87C530
022197 12/40
ROM MEMORY MAP Figure 4EA=1EA=064K
16K
64KFFFFh
0000h
FFFFh
0000h
3FFFh
ROM SIZE ADJUSTABLEDEFAULT = 16K BYTESROM SIZE IGNORED
USERSELECTABLE
DATA MEMORY ACCESSUnlike many 8051 derivatives, the DS87C530 contains
on–chip data memory. It also contains the standard 256
bytes of RAM accessed by direct instructions. These
areas are separate. The MOVX instruction accesses
the on–chip data memory. Although physically on–chip,
software treats this area as though it was located off–
chip. The 1KB of SRAM is between address 0000h and
03FFh.
Access to the on–chip data RAM is optional under soft-
ware control. When enabled by software, the data
SRAM is between 0000h and 03FFh. Any MOVX
instruction that uses this area will go to the on–chip RAM
while enabled. MOVX addresses greater than 03FFh
automatically go to external memory through Ports 0
and 2.
When disabled, the 1KB memory area is transparent to
the system memory map. Any MOVX directed to the
space between 0000h and FFFFh goes to the expanded
bus on Ports 0 and 2. This also is the default condition.
This default allows the DS87C530 to drop into an exist-
ing system that uses these addresses for other hard-
ware and still have full compatibility.
The on–chip data area is software selectable using two
bits in the Power Management Register at location C4h.
This selection is dynamically programmable. Thus
access to the on–chip area becomes transparent to
reach off–chip devices at the same addresses. The con-
trol bits are DME1 (PMR.1) and DME0 (PMR.0). They
have the following operation:
DATA MEMORY ACCESS CONTROL Table 3Notes on the status byte read at FFFCh with DME1, 0 = 1, 1: Bits 2–0 reflect the programmed status of the security lock
bits LB2–LB0. They are individually set to a logic 1 to correspond to a security lock bit that has been programmed.
These status bits allow software to verify that the part has been locked before running if desired. The bits are read only.
Note: After internal MOVX SRAM has been initialized, changing bits DEM0/1 will have no affect on the contents of the
SRAM.
DS87C530
022197 13/40
STRETCH MEMORY CYCLEThe DS87C530 allows software to adjust the speed of
off–chip data memory access. The micro is capable of
performing the MOVX in as few as two instruction
cycles. The on–chip SRAM uses this speed and any
MOVX instruction directed internally uses two cycles.
However, the time can be stretched for interface to
external devices. This allows access to both fast
memory and slow memory or peripherals with no glue
logic. Even in high–speed systems, it may not be neces-
sary or desirable to perform off–chip data memory
access at full speed. In addition, there are a variety of
memory mapped peripherals such as LCDs or UARTs
that are slow.
The Stretch MOVX is controlled by the Clock Control
Register at SFR location 8Eh as described below. It
allows the user to select a Stretch value between zero
and seven. A Stretch of zero will result in a two machine
cycle MOVX. A Stretch of seven will result in a MOVX of
nine machine cycles. Software can dynamically change
this value depending on the particular memory or
peripheral.
On reset, the Stretch value will default to a one resulting
in a three cycle MOVX for any external access. There-
fore, off–chip RAM access is not at full speed. This is a
convenience to existing designs that may not have fast
RAM in place. Internal SRAM access is always at full
speed regardless of the Stretch setting. When desiring
maximum speed, software should select a Stretch value
of zero. When using very slow RAM or peripherals,
select a larger Stretch value. Note that this affects data
memory only and the only way to slow program memory
(ROM) access is to use a slower crystal.
Using a Stretch value between one and seven causes
the microcontroller to stretch the read/write strobe and
all related timing. Also, setup and hold times are
increased by 1 clock when using any Stretch greater
than 0. This results in a wider read/write strobe and
relaxed interface timing, allowing more time for
memory/peripherals to respond. The timing of the vari-
able speed MOVX is in the Electrical Specifications.
Table 4 shows the resulting strobe widths for each
Stretch value. The memory Stretch uses the Clock Con-
trol Special Function Register at SFR location 8Eh. The
Stretch value is selected using bits CKCON.2–0. In the
table, these bits are referred to as M2 through M0. The
first Stretch (default) allows the use of common 120 ns
RAMs without dramatically lengthening the memory
access.
DATA MEMORY CYCLE STRETCH VALUES Table 4
CKCON.2–0RD OR WR STROBESTROBE WIDTH TIMEM1M0MEMORY CYCLESWIDTH IN CLOCKS@ 33 MHz002 (forced internal)260 ns013 (default external)4121 ns1048242 ns11512364 ns00616485 ns01720606 ns10824727 ns11928848 ns
DUAL DATA POINTERThe timing of block moves of data memory is faster
using the DS87C530 Dual Data Pointer (DPTR). The
standard 8051 DPTR is a 16–bit value that is used to
address off–chip data RAM or peripherals. In the
DS87C530, the standard data pointer is called DPTR,
located at SFR addresses 82h and 83h. These are the
standard locations. Using DPTR requires no modifica-
tion of standard code. The new DPTR at SFR 84h and
85h is called DPTR1. The DPTR Select bit (DPS)
chooses the active pointer. Its location is the lsb of the
SFR location 86h. No other bits in register 86h have any
effect and are 0. The user switches between data point-
ers by toggling the lsb of register 86h. The increment
(INC) instruction is the fastest way to accomplish this.
All DPTR–related instructions use the currently
selected DPTR for any activity. Therefore it takes only
one instruction to switch from a source to a destination
address. Using the Dual Data Pointer saves code from
needing to save source and destination addresses
when doing a block move. The software simply switches
between DPTR and 1 once software loads them. The
relevant register locations are as follows.
DS87C530
022197 14/40
DPL82hLow byte original DPTR
DPH83hHigh byte original DPTR
DPL184hLow byte new DPTR
DPH185hHigh byte new DPTR
DPS86h DPTR Select (lsb)
POWER MANAGEMENTAlong with the standard Idle and power down (Stop)
modes of the standard 80C52, the DS87C530 provides
a new Power Management Mode. This mode allows the
processor to continue functioning, yet to save power
compared with full operation. The DS87C530 also fea-
tures several enhancements to Stop mode that make it
more useful.
POWER MANAGEMENT MODE (PMM)Power Management Mode offers a complete scheme of
reduced internal clock speeds that allow the CPU to run
software but to use substantially less power. During
default operation, the DS87C530 uses four clocks per
machine cycle. Thus the instruction cycle rate is
(Clock/4). At 33 MHz crystal speed, the instruction cycle
speed is 8.25 MHz (33/4). In PMM, the microcontroller
continues to operate but uses an internally divided ver-
sion of the clock source. This creates a lower power
state without external components. It offers a choice of
two reduced instruction cycle speeds (and two clock
sources – discussed below). The speeds are (Clock/64)
and (Clock/1024).
Software is the only mechanism to invoke the PMM.
Table 5 illustrates the instruction cycle rate in PMM for
several common crystal frequencies. Since power con-
sumption is a direct function of operating speed, PMM 1
eliminates most of the power consumption while still
allowing a reasonable speed of processing. PMM 2 runs
very slowly and provides the lowest power consumption
without stopping the CPU. This is illustrated in Table 6.
Note that PMM provides a lower power condition than
Idle mode. This is because in Idle, all clocked functions
such as timers run at a rate of crystal divided by 4. Since
wake–up from PMM is as fast as or faster than from Idle
and PMM allows the CPU to operate (even if doing
NOPs), there is little reason to use Idle mode in new
designs.
INSTRUCTION CYCLE RATE Table 5
OPERATING CURRENT ESTIMATES IN PMM Table 6
DS87C530
022197 15/40
CRYSTALESS PMMA major component of power consumption in PMM is
the crystal amplifier circuit. The DS87C530 allows the
user to switch CPU operation to an internal ring oscilla-
tor and turn off the crystal amplifier. The CPU would then
have a clock source of approximately 2–4 MHz, divided
by either 4, 64, or 1024. The ring is not accurate, so soft-
ware can not perform precision timing. However, this
mode allows an additional saving of between 0.5 and
6.0 mA depending on the actual crystal frequency.
While this saving is of little use when running at 4 clocks
per instruction cycle, it makes a major contribution when
running in PMM1 or PMM2.
PMM OPERATIONSoftware invokes the PMM by setting the appropriate
bits in the SFR area. The basic choices are divider
speed and clock source. There are three speeds (4, 64,
and 1024) and two clock sources (crystal, ring). Both the
decisions and the controls are separate. Software will
typically select the clock speed first. Then, it will perform
the switch to ring operation if desired. Lastly, software
can disable the crystal amplifier if desired.
There are two ways of exiting PMM. Software can
remove the condition by reversing the procedure that
invoked PMM or hardware can (optionally) remove it. To
resume operation at a divide by 4 rate under software
control, simply select 4 clocks per cycle, then crystal
based operation if relevant. When disabling the crystal
as the time base in favor of the ring oscillator, there are
timing restrictions associated with restarting the crystal
operation. Details are described below.
There are three registers containing bits that are con-
cerned with PMM functions. They are Power Manage-
ment Register (PMR; C4h), Status (STATUS; C5h), and
External Interrupt Flag (EXIF; 91h)
Clock DividerSoftware can select the instruction cycle rate by select-
ing bits CD1 (PMR.7) and CD0 (PMR.6) as follows:0Reserved14 clocks (default)064 clocks11024 clocks
The selection of instruction cycle rate will take effect
after a delay of one instruction cycle. Note that the clock
divider choice applies to all functions including timers.
Since baud rates are altered, it will be difficult to conduct
serial communication while in PMM. There are minor
restrictions on accessing the clock selection bits. The
processor must be running in a 4 clock state to select
either 64 (PMM1) or 1024 (PMM2) clocks. This means
software cannot go directly from PMM1 to PMM2 or visa
versa. It must return to a 4 clock rate first.
SwitchbackTo return to a 4 clock rate from PMM, software can sim-
ply select the CD1 and CD0 clock control bits to the 4
clocks per cycle state. However, the DS87C530 pro-
vides several hardware alternatives for automatic
Switchback. If Switchback is enabled, then the
DS87C530 will automatically return to a 4 clock per
cycle speed when an interrupt occurs from an enabled,
valid external interrupt source. A Switchback will also
occur when a UART detects the beginning of a serial
start bit if the serial receiver is enabled (REN=1). Note
the beginning of a start bit does not generate an inter-
rupt; this occurs on reception of a complete serial word.
The automatic Switchback on detection of a start bit
allows hardware to correct baud rates in time for a
proper serial reception. A switchback will also occur
when a byte is written to the SBUF0 or SBUF1 for trans-
mission.
Switchback is enabled by setting the SWB bit (PMR.5)
to a 1 in software. For an external interrupt, Switchback
will occur only if the interrupt source could really gener-
ate the interrupt. For example, if INT0 is enabled but has
a low priority setting, then Switchback will not occur on
INT0 if the CPU is servicing a high priority interrupt.
StatusInformation in the Status register assists decisions
about switching into PMM. This register contains
information about the level of active interrupts and the
activity on the serial ports.
The DS87C530 supports three levels of interrupt prior-
ity. These levels are Power–fail, High, and Low. Bits
STATUS.7–5 indicate the service status of each level. If
PIP (Power–fail Interrupt Priority; STATUS.7) is a 1,
then the processor is servicing this level. If either HIP
DS87C530
022197 16/40
(High Interrupt Priority; STATUS.6) or LIP (Low Interrupt
Priority; STATUS.5) is high, then the corresponding
level is in service.
Software should not rely on a lower priority level inter-
rupt source to remove PMM (Switchback) when a
higher level is in service. Check the current priority ser-
vice level before entering PMM. If the current service
level locks out a desired Switchback source, then it
would be advisable to wait until this condition clears
before entering PMM.
Alternately, software can prevent an undesired exit from
PMM by entering a low priority interrupt service level
before entering PMM. This will prevent other low priority
interrupts from causing a Switchback.
Status also contains information about the state of the
serial ports. Serial Port Zero Receive Activity (SPRA0;
STATUS.0) indicates a serial word is being received on
Serial Port 0 when this bit is set to a 1. Serial Port Zero
Transmit Activity (SPTA0; STATUS.1) indicates that the
serial port is still shifting out a serial transmission. STA-
TUS.2 and STATUS.3 provide the same information for
Serial Port 1, respectively. These bits should be
interrogated before entering PMM1 or PMM2 to ensure
that no serial port operations are in progress. Changing
the clock divisor rate during a serial transmission or
reception will corrupt the operation.
Crystal/Ring OperationThe DS87C530 allows software to choose the clock
source as an independent selection from the instruction
cycle rate. The user can select crystal–based or ring
oscillator–based operation under software control.
Power–on reset default is the crystal (or external clock)
source. The ring may save power depending on the
actual crystal speed. To save still more power, software
can then disable the crystal amplifier. This process
requires two steps. Reversing the process also requires
two steps.
The XT/RG bit (EXIF.3) selects the crystal or ring as the
clock source. Setting XT/RG = 1 selects the crystal. Set-
ting XT/RG = 0 selects the ring. The RGMD (EXIF.2) bit
serves as a status bit by indicating the active clock
source. RGMD = 0 indicates the CPU is running from
the crystal. RGMD = 1 indicates it is running from the
ring. When operating from the ring, disable the crystal
amplifier by setting the XTOFF bit (PMR.3) to a 1. This
can only be done when XT/RG = 0.
When changing the clock source, the selection will take
effect after a one instruction cycle delay. This applies to
changes from crystal to ring and vise versa. However,
this assumes that the crystal amplifier is running. In
most cases, when the ring is active, software previously
disabled the crystal to save power. If ring operation is
being used and the system must switch to crystal opera-
tion, the crystal must first be enabled. Set the XTOFF bit
to a 0. At this time, the crystal oscillation will begin. The
DS87C530 then provides a warm–up delay to make cer-
tain that the frequency is stable. Hardware will set the
XTUP bit (STATUS.4) to a 1 when the crystal is ready for
use. Then software should write XT/RG to a 1 to begin
operating from the crystal. Hardware prevents writing
XT/RG to a 1 before XTUP = 1. The delay between
XTOFF = 0 and XTUP = 1 will be 65,536 crystal clocks in
addition to the crystal cycle startup time.
Switchback has no effect on the clock source. If soft-
ware selects a reduced clock divider and enables the
ring, a Switchback will only restore the divider speed.
The ring will remain as the time base until altered by soft-
ware. If there is serial activity, Switchback usually
occurs with enough time to create proper baud rates.
This is not true if the crystal is off and the CPU is running
from the ring. If sending a serial character that wakes
the system from crystaless PMM, then it should be a
dummy character of no importance with a subsequent
delay for crystal startup.
The following table is a summary of the bits relating to
PMM and its operation. The flow chart below illustrates
a typical decision set associated with PMM.
DS87C530
022197 17/40
PMM CONTROL AND STATUS BIT SUMMARY Table 7
DS87C530
022197 18/40
INVOKING AND CLEARING PMM Figure 3LOWEST POWER OPERATING STATE
ENTER POWER MANAGEMENT MODEEXITING POWER MANAGEMENT MODE
SOFTWARE DECIDES
TO EXIT
SWB=1 AND EXTERNAL
ACTIVITY OCCURS
DS87C530
022197 19/40
IDLE MODESetting the lsb of the Power Control register (PCON; 87h)
invokes the Idle mode. Idle will leave internal clocks,
serial ports and timers running. Power consumption
drops because the CPU is not active. Since clocks are
running, the Idle power consumption is a function of crys-
tal frequency. It should be approximately 1/2 of the opera-
tional power at a given frequency. The CPU can exit the
Idle state with any interrupt or a reset. Idle is available for
backward software compatibility. The system can now
reduce power consumption to below Idle levels by using
PMM1 or PMM2 and running NOPs.
STOP MODE ENHANCEMENTSSetting bit 1 of the Power Control register (PCON; 87h)
invokes the Stop mode. Stop mode is the lowest power
state since it turns off all internal clocking. The ICC of a
standard Stop mode is approximately 1 μA but is speci-
fied in the Electrical Specifications. The CPU will exit
Stop mode from an external interrupt or a reset condi-
tion. Internally generated interrupts (timer, serial port,
watchdog) are not useful since they require clocking
activity. One exception is that a real time clock interrupt
can cause the device to exit Stop mode. This provides a
very power efficient way of performing infrequent yet
periodic tasks.
The DS87C530 provides two enhancements to the Stop
mode. As documented below, the DS87C530 provides
a band–gap reference to determine Power–fail Interrupt
and Reset thresholds. The default state is that the
band–gap reference is off while in Stop mode. This
allows the extremely low power state mentioned above.
A user can optionally choose to have the band–gap
enabled during Stop mode. With the band–gap refer-
ence enabled, PFI and Power–fail reset are functional
and are a valid means for leaving Stop mode. This
allows software to detect and compensate for a brown–
out or power supply sag, even when in Stop mode.
In Stop mode with the band–gap enabled, ICC will be
approximately 50 μA compared with 1 μA with the
band–gap off. If a user does not require a Power–fail
Reset or Interrupt while in Stop mode, the band–gap
can remain disabled. Only the most power sensitive
applications should turn off the band–gap, as this
results in an uncontrolled power down condition.
The control of the band–gap reference is located in the
Extended Interrupt Flag register (EXIF; 91h). Setting
BGS (EXIF.0) to a 1 will keep the band–gap reference
enabled during Stop mode. The default or reset condi-
tion is with the bit at a logic 0. This results in the band–
gap being off during Stop mode. Note that this bit has no
control of the reference during full power, PMM, or Idle
modes.
The second feature allows an additional power saving
option while also making Stop easier to use. This is the
ability to start instantly when exiting Stop mode. It is the
internal ring oscillator that provides this feature. This
ring can be a clock source when exiting Stop mode in
response to an interrupt. The benefit of the ring oscilla-
tor is as follows.
Using Stop mode turns off the crystal oscillator and all
internal clocks to save power. This requires that the
oscillator be restarted when exiting Stop mode. Actual
start–up time is crystal dependent, but is normally at
least 4 ms. A common recommendation is 10 ms. In an
application that will wake–up, perform a short operation,
then return to sleep, the crystal start–up can be longer
than the real transaction. However, the ring oscillator
will start instantly. Running from the ring, the user can
perform a simple operation and return to sleep before
the crystal has even started. If a user selects the ring to
provide the start–up clock and the processor remains
running, hardware will automatically switch to the crys-
tal once a power–on reset interval (65536 clocks) has
expired. Hardware uses this value to assure proper
crystal start even though power is not being cycled.
The ring oscillator runs at approximately 2–4 MHz but
will not be a precise value. Do not conduct real–time
precision operations (including serial communication)
during this ring period. Figure 4 shows how the opera-
tion would compare when using the ring, and when
starting up normally. The default state is to exit Stop
mode without using the ring oscillator.
The RGSL – Ring Select bit at EXIF.1 (EXIF; 91h) con-
trols this function. When RGSL = 1, the CPU will use the
ring oscillator to exit Stop mode quickly. As mentioned
above, the processor will automatically switch from the
ring to the crystal after a delay of 65,536 crystal clocks.
For a 3.57 MHz crystal, this is approximately 18 ms. The
processor sets a flag called RGMD– Ring Mode,
located at EXIF.2, that tells software that the ring is
being used. The bit will be a logic 1 when the ring is in
use. Attempt no serial communication or precision tim-
ing while this bit is set, since the operating frequency is
not precise.
DS87C530
022197 20/40
RING OSCILLATOR EXIT FROM STOP MODE Figure 4ÎÎÎÎÎ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
CRYSTALOSCILLATION
POWER
CRYSTALOSCILLATION
RINGOSCILLATION
POWER
uC OPERATING
uC ENTERSSTOP MODEINTERRUPT;CLOCK STARTSCLOCKSTABLEuC ENTERSSTOP MODE
uC ENTERS
STOP MODE
INTERRUPT;
RING STARTS
uC ENTERS
STOP MODE
POWER SAVED
STOP MODE WITH RING STARTUPuC OPERATING
uC OPERATING
STOP MODE WITHOUT RING STARTUPNote: Diagram assumes that the operation following Stop requires less than 18 ms to complete.
EMI REDUCTIONThe DS87C530 allows software to reduce EMI. One of
the major contributors to radiated noise in an 8051
based system is the toggling of ALE. The DS87C530
allows software to disable ALE when not used by setting
the ALEOFF (PMR.2) bit to a 1. When ALEOFF = 1,
ALE will still toggle during an off–chip MOVX. However,
ALE will remain in a static when performing on–chip
memory access. The default state of ALEOFF = 0 so
ALE toggles with every instruction cycle.
PERIPHERAL OVERVIEWThe DS87C530 provides several of the most commonly
needed peripheral functions in microcomputer–based
systems. These new functions include a second serial
port, Power–fail Reset, Power–fail Interrupt, and a pro-
grammable Watchdog Timer. These are described
below, and more details are available in the High–
Speed Microcontroller User’s Guide.
SERIAL PORTSThe DS87C530 provides a serial port (UART) that is
identical to the 80C52. In addition it includes a second
hardware serial port that is a full duplicate of the stan-
dard one. This port optionally uses pins P1.2 (RXD1)
and P1.3 (TXD1). It has duplicate control functions
included in new SFR locations.
Both ports can operate simultaneously but can be at dif-
ferent baud rates or even in different modes. The second
serial port has similar control registers (SCON1; C0h,
SBUF1; C1h) to the original. The new serial port can only
use Timer 1 for timer generated baud rates.
