DS80C390 ,Dual CAN High-Speed MicroprocessorELECTRICAL CHARACTERISTICS (Note 10) PARAMETER SYMBOL MIN TYP MAX UNITS Supply Voltage V V 5.0 5.5 ..
DS80C390-FCR ,Dual CAN High-Speed Microprocessorapplications. Thisfeature allows software to switch from the standard machine cycle rate of 4 cloc ..
DS80C390FNR ,Dual CAN High-Speed Microprocessorfeatures to speed block data memory moves. Italso can adjust the speed of MOVX data memory access ..
DS80C390-FNR+ ,Dual CAN High-Speed MicroprocessorFEATURES The DS80C390 is a fast 8051-compatible 80C52 Compatible microprocessor with dual CAN 2.0 ..
DS80C390-QCR ,Dual CAN High-Speed Microprocessorfeatures two full-function Controller Area Network (CAN) 2.0B controllers. Status andcontrol regis ..
DS80C390-QCR+ ,Dual CAN High-Speed MicroprocessorAPPLICATIONS DS80C390-QCR+ 0°C to +70°C 68 PLCC Industrial Controls Agricultural Equipment DS80C390 ..
ECH8401 ,Medium Output MOSFETsAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage ..
ECH8402 ,Medium Output MOSFETsAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage ..
ECH8402 ,Medium Output MOSFETsOrdering number : ENN8148 ECH8402N-Channel Silicon MOSFETGeneral-Purpose Switching DeviceECH8402App ..
ECH8410 ,N-Channel Power MOSFET, 30V, 12A, 10mOhm, Single ECH8Maximum RatingsParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage V 30 VDSSGate-to-Sou ..
ECH8601 ,Nch+NchAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage ..
ECH8604 ,N CHANNEL MOS SILICON TRANSISTOR
DS80C390
Dual CAN High-Speed Microprocessor
GENERAL DESCRIPTION The DS80C390 is a fast 8051-compatible
microprocessor with dual CAN 2.0B controllers. The
redesigned processor core executes 8051
instructions up to 3X faster than the original for the
same crystal speed. The DS80C390 supports a
maximum crystal speed of 40MHz, resulting in
apparent execution speeds of 100MHz
(approximately 2.5X). An optional internal frequency
multiplier allows the microprocessor to operate at full
speed with a reduced crystal frequency, reducing
EMI. A hardware math accelerator further increases
the speed of 32-bit and 16-bit multiply and divide
operations as well as high-speed shift, normalization,
and accumulate functions.
The High-Speed Microcontroller User’s Guide and High-Speed
Microcontroller User’s Guide: DS80C390 Supplement must be
used in conjunction with this data sheet. Download both at:
/microcontrollers.
APPLICATIONS Industrial Controls Agricultural Equipment
Factory Automation Gaming Equipment
Medical Equipment Heating, Ventilation, and
Air Conditioning
FEATURES
80C52 Compatible
High-Speed Architecture
4kB Internal SRAM Usable as Program/
Data/Stack Memory
Enhanced Memory Architecture
Two Full-Function CAN 2.0B Controllers
Two Full-Duplex Hardware Serial Ports
Programmable IrDA Clock
High Integration Controller
16 Interrupt Sources with Six External
Available in 64-Pin LQFP, 68-Pin PLCC See page 29 for a complete list of features.
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS80C390-QCR 0°C to +70°C 68 PLCC
DS80C390-QCR+ 0°C to +70°C 68 PLCC
DS80C390-QNR -40°C to +85°C 68 PLCC
DS80C390-QNR+ -40°C to +85°C 68 PLCC
DS80C390-FCR 0°C to +70°C 64 LQFP
DS80C390-FCR+ 0°C to +70°C 64 LQFP
DS80C390-FNR -40°C to +85°C 64 LQFP
DS80C390-FNR+ -40°C to +85°C 64 LQFP
+Denotes a lead(Pb)-free/RoHS-compliant device.
PIN CONFIGURATIONS 61 9
10
26
27 43
60
44
Dallas Semiconductor DS80C390
PLCC 49
Dallas Semiconductor DS80C390
48 33
32
17
16 1
64
LQFP TOP VIEW
DS80C390
Dual CAN High-Speed
Microprocessor
DS80C390 Dual CAN High-Speed Microprocessor
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………………….-0.3V to (VCC + 0.5V)
Voltage Range on VCC Relative to Ground……………………………………………………………………-0.3V to +6.0V
Operating Temperature Range………………………………………………………………………………..-40°C to +85°C
Storage Temperature Range………………………………………………………………………………...-55°C to +125°C
Soldering Temperature…..……………………………………………………………………..See IPC/JEDEC J-STD-020
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS Supply Voltage VCC VRST 5.0 5.5 V
Power-Fail Warning VPFW 4.10 4.38 4.60 V
Minimum Operating Voltage VRST 3.85 4.13 4.35 V
Supply Current, Active Mode (Note 1) ICC 80 150 mA
Supply Current, Idle Mode (Note 2) IIDLE 40 75 mA
Supply Current, Stop Mode (Note 3) ISTOP 1 120 µA
Supply Current, Stop Mode, Bandgap Enabled (Note 3) ISPBG 150 350 µA
Input Low Level VIL -0.5 +0.8 V
Input High Level VIH 2.0 VCC +0.5 V
Input High Level for XTAL1, RST VIH2 0.7 x VCC VCC +0.5 V
Output Low Voltage for Port 1, 3, 4, 5 at IOL = 1.6mA VOL1 0.45 V
Output Low Voltage for Port 0, 1, 2, 4, 5, RD, WR, RSTOL, PSEN,
and ALE at IOL = 3.2mA (Note 5) VOL2 0.45 V
Output High Voltage for Port 1, 3, 4, 5 at IOH = -50µA (Note 4) VOH1 2.4 V
Output High Voltage for Port 1, 3, 4, 5 at IOH = -1.5mA (Note 6) VOH2 2.4 V
Output High Voltage for Port 0, 1, 2, 4, 5, RD, WR, RSTOL, PSEN,
and ALE at IOH = -8mA (Note 5, 7) VOH3 2.4 V
Input Low Current for Port 1, 3, 4, 5 at 0.45V (Note 8) IIL -55 µA
Logic 1 to 0 Transition Current for Port 1, 3, 4, 5 (Note 9) IT1 -650 µA
Input Leakage Current for Port 0 (Input Mode Only) IL -300 +300 µA
RST Pulldown Resistance RRST 50 170 kΩ
Note 1: Active current measured with 40MHz clock source on XTAL1, VCC = RST = 5.5V, all other pins disconnected.
Note 2: Idle mode current measured with 40MHz clock source on XTAL1, VCC= 5.5V, RST = EA = VSS, all other pins disconnected.
Note 3: Stop mode current measured with XTAL1 = RST = EA = VSS, VCC = 5.5V, all other pins disconnected.
Note 4: RST = VCC. This condition mimics operation of pins in I/O mode.
Note 5: Applies to port pins when they are used to address external memory or as CAN interface signals.
Note 6: This measurement reflects the port during a 0-to-1 transition in I/O mode. During this period a one-shot circuit drives the ports hard
for two clock cycles. If a port 4 or 5 pin is functioning in memory mode with pin state of 0 and the SFR bit contains a 1, changing
the pin to an I/O mode (by writing to P4CNT) will not enable the 2-cycle strong pullup. During Stop or Idle mode the pins switch to
I/O mode, and so port 2 and port 1 (in nonmultiplexed mode) will not exhibit the 2-cycle strong pullup when entering Stop or Idle
mode.
Note 7: Port 3 pins 3.6 and 3.7 have a stronger than normal pullup drive for one oscillator period following the transition of either the RD or
WR from a 0-to-1 transition.
Note 8: This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is
set to 1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin also have to overcome the
transition current.
Note 9: Ports 1(in I/O mode), 3, 4, and 5 source transition current when being pulled down externally. It reaches its maximum at
approximately 2V.
Note 10: Specifications to -40°C are guaranteed by design and not production tested.
DS80C390 Dual CAN High-Speed Microprocessor
AC ELECTRICAL CHARACTERISTICS—(MULTIPLEXED ADDRESS/DATA BUS)
(Note 10, Note 11)
PARAMETER SYMBOL CONDITIONS 40MHz VARIABLE CLOCK UNITS MIN MAX MIN MAX
Oscillator Frequency 1 / tCLCL External oscillator 0 40 0 40 MHz External crystal 1 40 1 40
ALE Pulse Width tLHLL 0.375 tMCS
- 5 ns
Port 0 Instruction Address or CE0---4
Valid to ALE Low tAVLL 0.125 tMCS - 5 ns
Address Hold After ALE Low tLLAX1 0.125 tMCS - 5 ns
ALE Low to Valid Instruction In tLLIV 0.625 tMCS - 20 ns
ALE Low to PSEN Low tLLPL 0.125 tMCS - 5 ns
PSEN Pulse Width tPLPH 0.5 tMCS - 8 ns
PSEN Low to Valid Instruction In tPLIV 0.5 tMCS - 20 ns
Input Instruction Hold After PSEN tPXIX 0 0 ns
Input Instruction Float After PSEN tPXIZ 0.25 tMCS - 5 ns
Port 0 Address to Valid Instruction In tAVIV1 0.75 tMCS - 22 ns
Port 2, 4 Address to Valid Instruction
In tAVIV2 0.875 tMCS - 30 ns
PSEN Low to Address Float tPLAZ 0 0 ns
Note 11:
All parameters apply to both commercial and industrial temperature operation unless otherwise noted. The value tMCS is a function
of the machine cycle clock in terms of the processor’s input clock frequency. These relationships are described in the Stretch Value
Timing table. All signals characterized with load capacitance of 80pF except Port 0, ALE, PSEN, RD, and WR with 100pF.
Interfacing to memory devices with float times (turn off times) over 25ns can cause bus contention. This does not damage the
parts, but causes an increase in operating current. Specifications assume a 50% duty cycle for the oscillator. Port 2 and ALE timing
changes in relation to duty cycle variation. Some AC timing characteristic drawings contain references to the CLK signal. This
waveform is provided to assist in determining the relative occurrence of events and cannot be used to determine the timing of
signals relative to the external clock. AC timing is characterized and guaranteed by design but is not production tested.
DS80C390 Dual CAN High-Speed Microprocessor
AC SYMBOLS
The DS80C390 uses timing parameters and symbols similar to the original 8051 family. The following list of timing
symbols is provided as an aid to understanding the timing diagrams.
SYMBOL FUNCTION Time Address Clock
CE Chip Enable Input Data Logic Level High Logic Level Low Instruction PSEN Output Data RD Signal Valid WR Signal No longer a valid logic level. Tri-State
Figure 1. Multiplexed External Program Memory Read Cycle
DS80C390 Dual CAN High-Speed Microprocessor
MOVX CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS) (Note 12)
PARAMETER SYMBOL MIN MAX UNITS
STRETCH
VALUES
CST (MD2:0)
MOVX ALE Pulse Width tLHLL2
0.375 tMCS - 5 ns CST = 0
0.5 tMCS - 5 ns 1 ≤ CST ≤ 3
1.5 tMCS - 10 ns 4 ≤ CST ≤ 7
Port 0 MOVX Address, CE0---4,
PCE0---4 Valid to ALE Low tAVLL2
0.125 tMCS - 5 ns CST = 0
0.25tMCS - 5 ns 1≤ CST ≤ 3
1.25 tMCS - 10 ns 4 ≤ CST ≤ 7
Address Hold After MOVX
Read/Write
tLLAX2
tLLAX3
0.25tMCS-5 ns CST = 0
0.125 tMCS - 5 ns 1≤ CST ≤ 3
1.25 tMCS - 5 ns 4 ≤ CST ≤ 7
RD Pulse Width tRLRH 0.5 tMCS - 6 ns CST = 0
CST x tMCS - 10 ns 1 ≤ CST ≤ 7
WR Pulse Width tWLWH 0.5 tMCS - 6 ns CST = 0
CST x tMCS - 10 ns 1 ≤ CST ≤ 7
RD Low to Valid Data In tRLDV 0.5 tMCS - 20 ns CST = 0 CST x tMCS - 25 ns 1 ≤ CST ≤ 7
Data Hold After Read tRHDX 0 ns
Data Float After Read tRHDZ 0.25 tMCS - 5 ns CST = 0 0.5tMCS - 5 ns 1 ≤ CST ≤ 3 1.5 tMCS - 5 ns 4 ≤ CST ≤ 7
ALE Low to Valid Data In tLLDV 0.625 tMCS - 20 ns CST = 0 (CST + 0.25) x tMCS - 20 ns 1 ≤ CST ≤ 3 (CST + 1.25) x tMCS - 20 ns 4 ≤ CST ≤ 7
Port 0 Address, Port 4 CE, Port 5
PCE to Valid Data In tAVDV1 0.75 tMCS - 26 ns CST = 0 (4CST + 0.5) x tMCS - 30 ns 1≤ CST ≤ 3 (4CST + 2.5) x tMCS - 30 ns 4 ≤ CST ≤ 7
Port 2, 4 Address to Valid Data In tAVDV2 0.75 tMCS - 30 ns CST = 0 (4CST + 0.5) x tMCS - 30 ns 1 ≤ CST ≤ 3 (4CST + 2.5) x tMCS - 30 ns 4 ≤ CST ≤ 7
ALE Low to RD or WR Low tLLWL
0.125 tMCS - 5 0.125 tMCS + 10 ns CST =0
0.25tMCS - 5 0.25tMCS + 10 ns 1 ≤ CST ≤ 3
1.25 tMCS - 5 1.25 tMCS + 10 ns 4 ≤ CST ≤ 7
Port 0 Address, Port 4 CE, Port 5
PCE to RD or WR Low tAVWL1
0.25 tMCS - 11 ns CST = 0
0.5tMCS - 11 ns 1 ≤ CST ≤ 3
2.5 tMCS - 11 ns 4 ≤ CST ≤ 7
Port 2, 4 Address to or WR Low tAVWL2
0.375 tMCS - 11 ns CST = 0
0.625tMCS - 11 ns 1 ≤ CST ≤ 3
2.625 tMCS - 11 ns 4 ≤ CST ≤ 7
Data Valid to WR Transition tQVWX -8 ns
Data Hold After WR High tWHQX
0.25 tMCS - 8 ns CST = 0
0.5tMCS - 10 ns 1 ≤ CST ≤ 3
1.5 tMCS - 10 ns 4 ≤ CST ≤ 7
RD Low to Address Float tRLAZ See Note 12
RD or WR High to ALE, Port 4 CE
or Port 5 PCE High tWHLH
-5 +10 ns CST = 0
0.25 tMCS - 7 0.25 tMCS + 5 ns 1 ≤ CST ≤ 3
1.25 tMCS - 7 1.25 tMCS +10 ns 4 ≤ CST ≤ 7
Note 12:
All parameters apply to both commercial and industrial temperature operation. CST is the stretch cycle value determined by the
MD2:0 bits. tMCS is a time period shown in the tMCS Time Periods table. All signals characterized with load capacitance of 80pF
except Port 0, ALE, PSEN, RD, and WR with 100pF. Interfacing to memory devices with float times over 25ns can cause bus
contention and an increase in operating current. Specifications assume a 50% duty cycle for the oscillator; port 2 and ALE timing
changes in relation to duty cycle variation. Some AC timing characteristic drawings show the CLK signal, provided to determine the
relative occurrence of events and not the timing of signals relative to the external clock. During the external addressing mode, weak
